Data prefetching and address pre-calculation through instruction pre-execution with two-step physical register deallocation. - Akihiro Yamamoto; Yusuke Tanaka 001; Hideki Ando; Toshio Shimada (MEDEA@PACT, 2007)

Two-Step Physical Register Deallocation for Data Prefetching and Address Pre-Calculation. - Akihiro Yamamoto; Yusuke Tanaka 001; Hideki Ando; Toshio Shimada (Inf. Media Technol., 2008)

Reducing register file size through instruction pre-execution enhanced by value prediction. - Yusuke Tanaka 001; Hideki Ando (ICCD, 2009)

Register File Size Reduction through Instruction Pre-Execution Incorporating Value Prediction. - Yusuke Tanaka 001; Hideki Ando (IEICE Trans. Inf. Syst., 2010)