Write-optimized reliable design of STT MRAM. - Yusung Kim 002; Sumeet Kumar Gupta; Sang Phill Park; Georgios Panagopoulos; Kaushik Roy 001 (ISLPED, 2012)

Spin Orbit Torque Based Electronic Neuron. - Abhronil Sengupta; Sri Harsha Choday; Yusung Kim 002; Kaushik Roy 001 (CoRR, 2014)

Failure Mitigation Techniques for 1T-1MTJ Spin-Transfer Torque MRAM Bit-cells. - Xuanyao Fong; Yusung Kim 002; Sri Harsha Choday; Kaushik Roy 001 (IEEE Trans. Very Large Scale Integr. Syst., 2014)

AWARE (Asymmetric Write Architecture With REdundant Blocks): A High Write Speed STT-MRAM Cache Architecture. - Kon-Woo Kwon; Sri Harsha Choday; Yusung Kim 002; Kaushik Roy 001 (IEEE Trans. Very Large Scale Integr. Syst., 2014)

Magnetic Tunnel Junction Mimics Stochastic Cortical Spiking Neurons. - Abhronil Sengupta; Priyadarshini Panda; Parami Wijesinghe; Yusung Kim 002; Kaushik Roy 001 (CoRR, 2015)

Exploring Spin Transfer Torque Devices for Unconventional Computing. - Kaushik Roy 001; Deliang Fan; Xuanyao Fong; Yusung Kim 002; Mrigank Sharad; Somnath Paul; Subho Chatterjee; Swarup Bhunia; Saibal Mukhopadhyay (IEEE J. Emerg. Sel. Topics Circuits Syst., 2015)

Spin-Transfer Torque Memories: Devices, Circuits, and Systems. - Xuanyao Fong; Yusung Kim 002; Rangharajan Venkatesan; Sri Harsha Choday; Anand Raghunathan; Kaushik Roy 001 (Proc. IEEE, 2016)

Spin-Transfer Torque Devices for Logic and Memory: Prospects and Perspectives. - Xuanyao Fong; Yusung Kim 002; Karthik Yogendra; Deliang Fan; Abhronil Sengupta; Anand Raghunathan; Kaushik Roy 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2016)

A 10nm SRAM Design using Gate-Modulated Self-Collapse Write Assist Enabling 175mV VMIN Reduction with Negligible Power Overhead. - Zheng Guo; Jami Wiedemer; Yusung Kim 002; Prithvee Sundararajan Ramamoorthy; Prateeksha Bindiganavile Sathyaprasad; Smita Shridharan; Daeyeon Kim; Eric Karl (VLSI Circuits, 2020)

Energy-Efficient High Bandwidth 6T SRAM Design on Intel 4 CMOS Technology. - Yusung Kim 002; Clifford Ong; Anandkumar Mahadevan Pillai; Harish Jagadeesh; Gwanghyeon Baek; Iqbal Rajwani; Zheng Guo; Eric Karl (IEEE J. Solid State Circuits, 2023)

15.2 A 2048x60m4 SRAM Design in Intel 4 with an Around-the-Array Power-Delivery Scheme Using PowerVia. - Daeyeon Kim; Yusung Kim 002; Ayush Shrivastava; Gyusung Park; Anandkumar Mahadevan Pillai; Kunal Bannore; Tri Doan; Muktadir Rahman; Gwanghyeon Baek; Clifford Ong; Xiaofei Wang; Zheng Guo; et al. (ISSCC, 2024)

29.2 A 0.021µm2 High-Density SRAM in Intel-18A-RibbonFET Technology with PowerVia-Backside Power Delivery. - Xiaofei Wang; Yusung Kim 002; Gwanghyeon Baek; Kunal Girish Bannore; Kaushal Dave; Arash Joushaghani; Narae Kang; Minwoo Ko; Anandkumar Mahadevan Pillai; Hema Chandra Prakash Movva; Gyusung Park; Muktadir Rahman; et al. (ISSCC, 2025)