A 298-fJ/writecycle 650-fJ/readcycle 8T three-port SRAM in 28-nm FD-SOI process technology for image processor. - Haruki Mori; Tomoki Nakagawa; Yuki Kitahara; Yuta Kawamoto; Kenta Takagi; Shusuke Yoshimoto; Shintaro Izumi; Koji Nii; Hiroshi Kawaguchi 001; Masahiko Yoshimoto (CICC, 2015)

Capacitively coupled ECG sensor using a single electrode with adaptive power-line noise cancellation. - Yuta Kawamoto; Shintaro Izumi; Yoshito Tanaka; Hiroshi Kawaguchi 001; Masahiko Yoshimoto (BHI, 2016)

Adaptive noise cancellation method for capacitively coupled ECG sensor using single insulated electrode. - Yoshito Tanaka; Shintaro Izumi; Yuta Kawamoto; Hiroshi Kawaguchi 001; Masahiko Yoshimoto (BioCAS, 2016)

An low-energy 8T dual-port SRAM for image processor with selective sourceline drive scheme in 28-nm FD-SOI process technology. - Haruki Mori; Tomoki Nakagawa; Yuki Kitahara; Yuta Kawamoto; Kenta Takagi; Shusuke Yoshimoto; Shintaro Izumi; Hiroshi Kawaguchi 001; Masahiko Yoshimoto (ICECS, 2016)

A 28-nm FD-SOI 8T Dual-Port SRAM for Low-Energy Image Processor With Selective Sourceline Drive Scheme. - Haruki Mori; Tomoki Nakagawa; Yuki Kitahara; Yuta Kawamoto; Kenta Takagi; Shusuke Yoshimoto; Shintaro Izumi; Hiroshi Kawaguchi 001; Masahiko Yoshimoto (IEEE Trans. Circuits Syst. I Regul. Pap., 2019)

Model-Checking in the Loop Model-Based Testing for Automotive Operating Systems. - Toshiaki Aoki; Aritoshi Hata; Kazusato Kanamori; Satoshi Tanaka; Yuta Kawamoto; Yasuhiro Tanase; Masumi Imai; Fumiya Shigemitsu; Masaki Gondo; Tomoji Kishi (CoRR, 2023)