A Low-Latency DMR Architecture with Efficient Recovering Scheme Exploiting Simultaneously Copiable SRAM. - Go Matsukawa; Yohei Nakata; Yuta Kimi; Yasuo Sugure; Masafumi Shimozawa; Shigeru Oho; Hiroshi Kawaguchi 001; Masahiko Yoshimoto (ARCS Workshops, 2014)

A 40-nm resilient cache memory for dynamic variation tolerance with bit-enhancing memory and on-chip diagnosis structures delivering ×91 failure rate improvement. - Yohei Nakata; Yuta Kimi; Shunsuke Okumura; Jinwook Jung; Takuya Sawada; Taku Toshikawa; Makoto Nagata; Hirofumi Nakano; Makoto Yabuuchi; Hidehiro Fujiwara; Koji Nii; Hiroyuki Kawai; et al. (ISQED, 2014)

A 40-nm Resilient Cache Memory for Dynamic Variation Tolerance Delivering ×91 Failure Rate Improvement under 35% Supply Voltage Fluctuation. - Yohei Nakata; Yuta Kimi; Shunsuke Okumura; Jinwook Jung; Takuya Sawada; Taku Toshikawa; Makoto Nagata; Hirofumi Nakano; Makoto Yabuuchi; Hidehiro Fujiwara; Koji Nii; Hiroyuki Kawai; et al. (IEICE Trans. Electron., 2014)

Analysis of Soft Error Propagation Considering Masking Effects on Re-Convergent Path. - Yuta Kimi; Go Matsukawa; Shuhei Yoshida; Shintaro Izumi; Hiroshi Kawaguchi 001; Masahiko Yoshimoto (ATS, 2015)

An accurate soft error propagation analysis technique considering temporal masking disablement. - Yuta Kimi; Go Matsukawa; Shuhei Yoshida; Shintaro Izumi; Hiroshi Kawaguchi 001; Masahiko Yoshimoto (IOLTS, 2015)

A Low-Latency DMR Architecture with Fast Checkpoint Recovery Scheme. - Go Matsukawa; Yohei Nakata; Yasuo Sugure; Shigeru Oho; Yuta Kimi; Masafumi Shimozawa; Shuhei Yoshida; Hiroshi Kawaguchi 001; Masahiko Yoshimoto (IEICE Trans. Electron., 2015)

Error Propagation Analysis for Single Event Upset considering Masking Effects on Re-Convergent Path. - Go Matsukawa; Yuta Kimi; Shuhei Yoshida; Shintaro Izumi; Hiroshi Kawaguchi 001; Masahiko Yoshimoto (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2016)