Performance Evaluation of Software-based Error Detection Mechanisms for Localizing Electrical Timing Failures under Dynamic Supply Noise. - Yutaka Masuda; Masanori Hashimoto; Takao Onoye (ICCAD, 2015)

Stochastic timing error rate estimation under process and temporal variations. - Shoichi Iizuka; Yutaka Masuda; Masanori Hashimoto; Takao Onoye (ITC, 2015)

Critical path isolation for time-to-failure extension and lower voltage operation. - Yutaka Masuda; Masanori Hashimoto; Takao Onoye (ICCAD, 2016)

Hardware-simulation correlation of timing error detection performance of software-based error detection mechanisms. - Yutaka Masuda; Masanori Hashimoto; Takao Onoye (IOLTS, 2016)

Performance Evaluation of Software-Based Error Detection Mechanisms for Supply Noise Induced Timing Errors. - Yutaka Masuda; Takao Onoye; Masanori Hashimoto (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2017)

MTTF-aware design methodology of error prediction based adaptively voltage-scaled circuits. - Yutaka Masuda; Masanori Hashimoto (ASP-DAC, 2018)

Comparing voltage adaptation performance between replica and in-situ timing monitors. - Yutaka Masuda; Jun Nagayama; Hirotaka Takeno; Yoshimasa Ogawa; Yoichi Momiyama; Masanori Hashimoto (ICCAD, 2018)

Activation-Aware Slack Assignment for Time-to-Failure Extension and Power Saving. - Yutaka Masuda; Takao Onoye; Masanori Hashimoto (IEEE Trans. Very Large Scale Integr. Syst., 2018)

An Optical Neural Network Architecture based on Highly Parallelized WDM-Multiplier-Accumulator. - Tohru Ishihara; Jun Shiomi; Naoki Hattori; Yutaka Masuda; Akihiko Shinya; Masaya Notomi (PHOTONICS@SC, 2019)

MTTF-Aware Design Methodology of Adaptively Voltage Scaled Circuit with Timing Error Predictive Flip-Flop. - Yutaka Masuda; Masanori Hashimoto (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2019)

Real-Time Minimum Energy Point Tracking Using a Predetermined Optimal Voltage Setting Strategy. - Khyati Kiyawat; Yutaka Masuda; Jun Shiomi; Tohru Ishihara (ISVLSI, 2020)

Critical Path Isolation and Bit-Width Scaling Are Highly Compatible for Voltage Over-Scalable Design. - Yutaka Masuda; Jun Nagayama; TaiYu Cheng; Tohru Ishihara; Yoichi Momiyama; Masanori Hashimoto (DATE, 2021)

Dynamic Verification of Approximate Computing Circuits using Coverage-based Grey-box Fuzzing. - Kazuki Yoshisue; Yutaka Masuda; Tohru Ishihara (IOLTS, 2021)

Integration of Minimum Energy Point Tracking and Soft Real-Time Scheduling for Edge Computing. - Takumi Komori; Yutaka Masuda; Jun Shiomi; Tohru Ishihara (ISQED, 2021)

Neural Network Calculations at the Speed of Light Using Optical Vector-Matrix Multiplication and Optoelectronic Activation. - Naoki Hattori; Jun Shiomi; Yutaka Masuda; Tohru Ishihara; Akihiko Shinya; Masaya Notomi (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2021)

An Accuracy Reconfigurable Vector Accelerator Based on Approximate Logarithmic Multipliers. - Lingxiao Hou; Yutaka Masuda; Tohru Ishihara (ASP-DAC, 2022)

Power-aware pruning for ultrafast, energy-efficient, and accurate optical neural network design. - Naoki Hattori; Yutaka Masuda; Tohru Ishihara; Akihiko Shinya; Masaya Notomi (DAC, 2022)

Optoelectronic Implementation of Compact and Power-efficient Recurrent Neural Networks. - Taisei Ichikawa; Yutaka Masuda; Tohru Ishihara; Akihiko Shinya; Masaya Notomi (ISVLSI, 2022)

DVFS Virtualization for Energy Minimization of Mixed-Criticality Dual-OS Platforms. - Takumi Komori; Yutaka Masuda; Tohru Ishihara (RTCSA, 2022)

Activation-Aware Slack Assignment Based Mode-Wise Voltage Scaling for Energy Minimization. - TaiYu Cheng; Yutaka Masuda; Jun Nagayama; Yoichi Momiyama; Jun Chen; Masanori Hashimoto (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2022)

Approximate Minimum Energy Point Tracking and Task Scheduling for Energy-Efficient Real-Time Computing. - Takumi Komori; Yutaka Masuda; Jun Shiomi; Tohru Ishihara (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2022)

Low-Power Design Methodology of Voltage Over-Scalable Circuit with Critical Path Isolation and Bit-Width Scaling. - Yutaka Masuda; Jun Nagayama; TaiYu Cheng; Tohru Ishihara; Yoichi Momiyama; Masanori Hashimoto (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2022)

An Efficient Fault Injection Algorithm for Identifying Unimportant FFs in Approximate Computing Circuits. - Jiaxuan Lu; Yutaka Masuda; Tohru Ishihara (DATE, 2023)

Feedback-Tuned Fuzzing for Accelerating Quality Verification of Approximate Computing Design. - Yusei Honda; Yutaka Masuda; Tohru Ishihara (IOLTS, 2023)

A Standard Cell Memory Based on 2T Gain Cell DRAM for Memory-Centric Accelerator Design. - Tai-Feng Chen; Yutaka Masuda; Tohru Ishihara (SOCC, 2023)

An Accuracy Reconfigurable Vector Accelerator based on Approximate Logarithmic Multipliers for Energy-Efficient Computing. - Lingxiao Hou; Yutaka Masuda; Tohru Ishihara (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2023)

Dynamic Verification Framework of Approximate Computing Circuits using Quality-Aware Coverage-Based Grey-Box Fuzzing. - Yutaka Masuda; Yusei Honda; Tohru Ishihara (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2023)

Identification of Redundant Flip-Flops Using Fault Injection for Low-Power Approximate Computing Circuits. - Jiaxuan Lu; Yutaka Masuda; Tohru Ishihara (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2024)

Virtualizing DVFS for Energy Minimization of Embedded Dual-OS Platform. - Takumi Komori; Yutaka Masuda; Tohru Ishihara (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2024)

Piecewise-Linear Approximation of Self-Attention and Its Accuracy-Aware Training for Area-Efficient Vision Transformer Inference Accelerator. - Teppei Kawamura; Yutaka Masuda; Tohru Ishihara (ISQED, 2025)

Optoelectronic Pipeline Architecture of Convolutional RNN for Energy Efficient Inference at the Speed of Light. - Chunlu Wang; Yutaka Masuda; Tohru Ishihara (IEICE Trans. Electron., 2025)