Register-Transfer Module Selection for Sub-Micron ASIC Design. - Vasily G. Moshnyaga; Yutaka Mori; Keikichi Tamaru (IEICE Trans. Inf. Syst., 1995)

Diagonal routing in high performance microprocessor design. - Noriyuki Ito; Hideaki Katagiri; Ryoichi Yamashita; Hiroshi Ikeda; Hiroyuki Sugiyama; Hiroaki Komatsu; Yoshiyasu Tanamura; Akihiro Yoshitake; Kazuhiro Nonomura; Kinya Ishizaka; Hiroaki Adachi; Yutaka Mori; et al. (ASP-DAC, 2006)

High-Speed Interconnect for a Multiprocessor Server Using Over 1Tb/s Crossbar. - Jun Yamada; Hiroyuki Adachi; Yutaka Mori; Akihiko Harada; Seishi Okada; Hisashige Ando (ISSCC, 2006)

Linear and nonlinear impairments when adding and dropping superchannels in an elastic optical network. - Takuya Nakagawa; Yutaka Mori; Koichi Maru; Haruna Matsushita; Masahiko Jinno (APCC, 2015)

Unified architecture and design methodology for integrated SDM-WSS employing PLC-based spatial beam transformer array for various types of SDM fibers. - Masahiko Jinno; Yutaka Mori (OFC, 2016)

Effects of Adding/Dropping Nyquist WDM Superchannels on Linear and Nonlinear Transmission Impairments in an Elastic Optical Network. - Masahiko Jinno; Takuya Nakagawa; Yutaka Mori; Koichi Maru; Haruna Matsushita (IEICE Trans. Commun., 2016)

Unified Architecture of an Integrated SDM-WSS Employing a PLC-Based Spatial Beam Transformer Array for Various Types of SDM Fibers. - Masahiko Jinno; Yutaka Mori (JOCN, 2017)

Feasibility Demonstration of Integrated Fractioanal Joint Switching WSS Applicable for Few-Mode Multicore Fiber. - Yutaka Mori; Kosuke Yamashita; Masahiko Jinno (PSC, 2018)