Toward Scalable Superconducting Quantum Computer Implementation. - Yutaka Tabuchi; Shuhei Tamate; Yasunobu Nakamura (IEICE Trans. Electron., 2019)

How Many Trials Do We Need for Reliable NISQ Computing? - Teruo Tanimoto; Shuhei Matsuo; Satoshi Kawakami; Yutaka Tabuchi; Masao Hirokawa; Koji Inoue (ISVLSI, 2020)

Practical Error Modeling Toward Realistic NISQ Simulation. - Teruo Tanimoto; Shuhei Matsuo; Satoshi Kawakami; Yutaka Tabuchi; Masao Hirokawa; Koji Inoue (ISVLSI, 2020)

QECOOL: On-Line Quantum Error Correction with a Superconducting Decoder for Surface Code. - Yosuke Ueno; Masaaki Kondo; Masamitsu Tanaka; Yasunari Suzuki; Yutaka Tabuchi (DAC, 2021)

Superconducting quantum computer: a hint for building architectures. - Yutaka Tabuchi; Shuhei Tamate; Shinichi Yorozu (VLSI Circuits, 2021)

FPL Demo: A Flexible and Scalable Quantum-Classical Interface based on FPGAs. - Takefumi Miyoshi; Keisuke Koike; Shinichi Morisaka; Hidehisa Shiomi; Kazuhisa Ogawa; Yutaka Tabuchi; Makoto Negoro (FPL, 2022)

QULATIS: A Quantum Error Correction Methodology toward Lattice Surgery. - Yosuke Ueno; Masaaki Kondo; Masamitsu Tanaka; Yasunari Suzuki; Yutaka Tabuchi (HPCA, 2022)

NEO-QEC: Neural Network Enhanced Online Superconducting Decoder for Surface Codes. - Yosuke Ueno; Masaaki Kondo; Masamitsu Tanaka; Yasunari Suzuki; Yutaka Tabuchi (CoRR, 2022)

Toward Realization of Scalable Packaging and Wiring for Large-Scale Superconducting Quantum Computers. - Shuhei Tamate; Yutaka Tabuchi; Yasunobu Nakamura (IEICE Trans. Electron., 2022)

A Fully Pipelined Architecture of Quantum-Classical Interface for Realizing Fault-Tolerant Quantum Computer. - Takefumi Miyoshi; Keisuke Koike; Shinichi Morisaka; Hidehisa Shiomi; Ryo Matsuda; Kazuhisa Ogawa; Yutaka Tabuchi; Makoto Negoro (QCE, 2023)

Inter-Temperature Bandwidth Reduction in Cryogenic QAOA Machines. - Yosuke Ueno; Yuna Tomida; Teruo Tanimoto; Masamitsu Tanaka; Yutaka Tabuchi; Koji Inoue; Hiroshi Nakamura (IEEE Comput. Archit. Lett., 2024)

SFQ counter-based precomputation for large-scale cryogenic VQE machines. - Yosuke Ueno; Satoshi Imamura; Yuna Tomida; Teruo Tanimoto; Masamitsu Tanaka; Yutaka Tabuchi; Koji Inoue; Hiroshi Nakamura (CoRR, 2024)

C3-VQA: Cryogenic Counter-based Co-processor for Variational Quantum Algorithms. - Yosuke Ueno; Satoshi Imamura; Yuna Tomida; Teruo Tanimoto; Masamitsu Tanaka; Yutaka Tabuchi; Koji Inoue; Hiroshi Nakamura (CoRR, 2024)

High-Performance and Scalable Fault-Tolerant Quantum Computation with Lattice Surgery on a 2.5D Architecture. - Yosuke Ueno; Taku Saito; Teruo Tanimoto; Yasunari Suzuki; Yutaka Tabuchi; Shuhei Tamate; Hiroshi Nakamura (CoRR, 2024)

Toward Scalable Heterogeneous Controller System for Various Quantum Computer by Using Multiple FPGAs. - Takefumi Miyoshi; Keisuke Koike; Shinichi Morisaka; Yuuya Sugita; Toshi Sumida; Yutaka Tabuchi; Makoto Negoro; Hidehisa Shiomi; Ippei Nakamura; Takafumi Tomita; Sylvain De Léséleuc; Atsushi Noguchi; et al. (ICCE, 2025)