Folded Fat H-Tree: An Interconnection Topology for Dynamically Reconfigurable Processor Array. - Yutaka Yamada; Hideharu Amano; Michihiro Koibuchi; Akiya Jouraku; Kenichiro Anjo; Katsunobu Nishimura (EUC, 2004)

Implementing and Evaluating Stream Applications on the Dynamically Reconfigurable Processor. - Noriaki Suzuki; Shunsuke Kurotaki; Masayasu Suzuki; Naoto Kaneko; Yutaka Yamada; Katsuaki Deguchi; Yohei Hasegawa; Hideharu Amano; Kenichiro Anjo; Masato Motomura; Kazutoshi Wakabayashi; Takeo Toi; et al. (FCCM, 2004)

Stream applications on the dynamically reconfigurable processor. - Masayasu Suzuki; Yohei Hasegawa; Yutaka Yamada; Naoto Kaneko; Katsuaki Deguchi; Hideharu Amano; Kenichiro Anjo; Masato Motomura; Kazutoshi Wakabayashi; Takao Toi; Toru Awashima (FPT, 2004)

BLACK-BUS: A New Data-Transfer Technique Using Local Address on Networks-on-Chips. - Kenichiro Anjo; Yutaka Yamada; Michihiro Koibuchi; Akiya Jouraku; Hideharu Amano (IPDPS, 2004)

Non-Minimal Routing Strategy for Application-Specific Networks-on-Chips. - Hiroki Matsutani; Michihiro Koibuchi; Yutaka Yamada; Akiya Jouraku; Hideharu Amano (ICPP Workshops, 2005)

Evaluation of vibration in many positions by SOM. - Nobuaki Kamimoto; Yutaka Yamada; Masami Kitamura; Kiyoshi Nishikawa (Artif. Life Robotics, 2005)

An implementation of hardware accelerator using dynamically reconfigurable architecture. - Takashi Yoshikawa; Yutaka Yamada; Shigehiro Asano (Hot Chips Symposium, 2006)

A Simple Data Transfer Technique Using Local Address for Networks-on-Chips. - Michihiro Koibuchi; Kenichiro Anjo; Yutaka Yamada; Akiya Jouraku; Hideharu Amano (IEEE Trans. Parallel Distributed Syst., 2006)

Fat H-Tree: A Cost-Efficient Tree-Based On-Chip Network. - Hiroki Matsutani; Michihiro Koibuchi; Yutaka Yamada; D. Frank Hsu; Hideharu Amano (IEEE Trans. Parallel Distributed Syst., 2009)

FlexGrip™: A small and high-performance programmable hardware for highly sequential application. - Takashi Yoshikawa; Fumihiko Hyuga; Masayuki Tokunaga; Yutaka Yamada; Shigehiro Asano (COOL Chips, 2011)

Virtual Screening for Ligands of the Insect Molting Hormone Receptor. - Toshiyuki Harada; Yoshiaki Nakagawa; Takehiko Ogura; Yutaka Yamada; Takehiro Ohe; Hisashi Miyagawa (J. Chem. Inf. Model., 2011)

18.2 A 1.9TOPS and 564GOPS/W heterogeneous multicore SoC with color-based object classification accelerator for image-recognition applications. - Jun Tanabe; Toru Sano; Yutaka Yamada; Tomoki Watanabe; Mayu Okumura; Manabu Nishiyama; Tadakazu Nomura; Kazushige Oma; Nobuhiro Sato; Moriyasu Banno; Hiroo Hayashi; Takashi Miyamori (ISSCC, 2015)

Performance Prediction Method of Examinees Based on Matrix Completion. - Yutaka Yamada; Takahiro Ogawa 001; Miki Haseyama (GCCE, 2019)

A 20.5TOPS and 217.3GOPS/mm2 Multicore SoC with DNN Accelerator and Image Signal Processor Complying with ISO26262 for Automotive Applications. - Yutaka Yamada; Toru Sano; Yasuki Tanabe; Yutaro Ishigaki; Soichiro Hosoda; Fumihiko Hyuga; Akira Moriya; Ryuji Hada; Atsushi Masuda; Masato Uchiyama; Tomohiro Koizumi; Takanori Tamai; et al. (ISSCC, 2019)

A 20.5 TOPS Multicore SoC With DNN Accelerator and Image Signal Processor for Automotive Applications. - Yutaka Yamada; Masato Uchiyama; Masashi Jobashi; Tomohiro Koizumi; Takanori Tamai; Nobuhiro Sato; Jun Tanabe; Katsuyuki Kimura; Yoshinari Ojima; Ryusuke Murakami; Takashi Yoshikawa; Toru Sano; et al. (IEEE J. Solid State Circuits, 2020)

Trend Prediction of Students' Mock Examination Results Using Matrix Completion. - Yutaka Yamada; Keisuke Maeda; Takahiro Ogawa 001; Miki Haseyama (GCCE, 2022)