HC-Sim: a fast and exact l1 cache simulator with scratchpad memory co-simulation support. - Yu-Ting Chen 003; Jason Cong; Glenn Reinman (CODES+ISSS, 2011)

Dynamically reconfigurable hybrid cache: An energy-efficient last-level cache design. - Yu-Ting Chen 003; Jason Cong; Hui Huang 001; Bin Liu 006; Chunyue Liu; Miodrag Potkonjak; Glenn Reinman (DATE, 2012)

Static and dynamic co-optimizations for blocks mapping in hybrid caches. - Yu-Ting Chen 003; Jason Cong; Hui Huang 001; Chunyue Liu; Raghu Prabhakar; Glenn Reinman (ISLPED, 2012)

Accelerator-rich CMPs: From concept to real hardware. - Yu-Ting Chen 003; Jason Cong; Mohammad Ali Ghodrat; Muhuan Huang; Chunyue Liu; Bingjun Xiao; Yi Zou (ICCD, 2013)

A Novel High-Throughput Acceleration Engine for Read Alignment. - Yu-Ting Chen 003; Jason Cong; Jie Lei 001; Peng Wei 004 (FCCM, 2015)

Interconnect synthesis of heterogeneous accelerators in a shared memory architecture. - Yu-Ting Chen 003; Jason Cong (ISLPED, 2015)

ARACompiler: a prototyping flow and evaluation framework for accelerator-rich architectures. - Yu-Ting Chen 003; Jason Cong; Bingjun Xiao (ISPASS, 2015)

Customizable Computing - Yu-Ting Chen 003; Jason Cong; Michael Gill; Glenn Reinman; Bingjun Xiao (Morgan & Claypool Publishers, 2015)

The SMEM Seeding Acceleration for DNA Sequence Alignment. - Mau-Chung Frank Chang; Yu-Ting Chen 003; Jason Cong; Po-Tsang Huang; Chun-Liang Kuo; Cody Hao Yu (FCCM, 2016)

When Spark Meets FPGAs: A Case Study for Next-Generation DNA Sequencing Acceleration. - Yu-Ting Chen 003; Jason Cong; Zhenman Fang; Jie Lei 001; Peng Wei 004 (FCCM, 2016)

ARAPrototyper: Enabling Rapid Prototyping and Evaluation for Accelerator-Rich Architecture (Abstact Only). - Yu-Ting Chen 003; Jason Cong; Zhenman Fang; Peipei Zhou 001 (FPGA, 2016)

A High-throughput Architecture for Lossless Decompression on FPGA Designed Using HLS (Abstract Only). - Jie Lei 001; Yu-Ting Chen 003; Yunsong Li; Jason Cong (FPGA, 2016)

ARAPrototyper: Enabling Rapid Prototyping and Evaluation for Accelerator-Rich Architectures. - Yu-Ting Chen 003; Jason Cong; Zhenman Fang; Bingjun Xiao; Peipei Zhou 001 (CoRR, 2016)

Memory System Optimizations for Customized Computing - From Single-Chip to Datacenter. - Yu-Ting Chen 003 (2016)