An on-chip waveform capturing technique pursuing minimum cost of integration. - Yuuki Araga; Takushi Hashida; Makoto Nagata (ISCAS, 2010)

In-tier diagnosis of power domains in 3D TSV ICs. - Yuuki Araga; Makoto Nagata; Geert Van der Plas; Jaemin Kim; Nikolaos Minas; Pol Marchal; Youssef Travaly; Michael Libois; Antonio La Manna; Wenqi Zhang; Eric Beyne (3DIC, 2011)

A diagnosis testbench of analog IP cores against on-chip environmental disturbances. - Takushi Hashida; Yuuki Araga; Makoto Nagata (VTS, 2011)

A Diagnosis Testbench of Analog IP Cores for Characterization of Substrate Coupling Strength. - Takushi Hashida; Yuuki Araga; Makoto Nagata (IEICE Trans. Electron., 2011)

Noise analysis using on-chip waveform monitor in bandgap voltage references. - Akitaka Murata; Shuji Agatsuma; Daisaku Ikoma; Kouji Ichikawa; Takahiro Tsuda; Makoto Nagata; Kumpei Yoshikawa; Yuuki Araga; Yuji Harada (EMC Compo, 2013)

Performance Evaluation of Probing Front-End Circuits for On-Chip Noise Monitoring. - Yuuki Araga; Nao Ueda; Yasumasa Takagi; Makoto Nagata (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2013)

Substrate monitoring system for inspecting defects in TSV-based data buses. - Yuuki Araga; Kikuchi Katsuya; Masahiro Aoyagi (3DIC, 2014)

Guard-ring monitoring system for inspecting defects in TSV-based data buses. - Yuuki Araga; Kikuchi Katsuya; Masahiro Aoyagi (3DIC, 2015)

A study on substrate noise coupling among TSVs in 3D chip stack. - Yuuki Araga; Makoto Nagata; Joeri De Vos; Geert Van der Plas; Eric Beyne (IEICE Electron. Express, 2018)

Electrostatic Shield TSVs to Suppress Coupling Among Stacked ICs. - Yuuki Araga; Kikuchi Katsuya; Masahiro Aoyagi (3DIC, 2019)

Over-the-top Si Interposer Embedding Backside Buried Metal PDN to Reduce Power Supply Impedance of Large Scale Digital ICs. - Takuji Miki; Makoto Nagata; Akihiro Tsukioka; Noriyuki Miura; Takaaki Okidono; Yuuki Araga; Naoya Watanabe; Haruo Shimamoto; Katsuya Kikuchi (3DIC, 2019)

A Si-Backside Protection Circuits Against Physical Security Attacks on Flip-Chip Devices. - Takuji Miki; Makoto Nagata; Hiroki Sonoda; Noriyuki Miura; Takaaki Okidono; Yuuki Araga; Naoya Watanabe; Haruo Shimamoto; Katsuya Kikuchi (A-SSCC, 2019)

Landside capacitor efficacy among multi-chip-module using Si-interposer. - Yuuki Araga; Ryo Kasai; Daisuke Tanaka; Yoshihide Murakami; Kyoshi Mihara; Kazuo Makida; Hiroki Sonoda; Makoto Nagata; Naoya Watanabe; Haruo Shimamoto; Katsuya Kikuchi (IEICE Electron. Express, 2021)

Analysis and evaluation of noise coupling between through-silicon-vias. - Yuuki Araga; Naoya Watanabe; Haruo Shimamoto; Katsuya Kikuchi (IEICE Electron. Express, 2021)