A Yield and Speed Enhancement Technique Using Reconfigurable Devices Against Within-Die Variations on the Nanometer Regime. - Kazutoshi Kobayashi; Manabu Kotani; Kazuya Katsuki; Y. Takatsukasa; K. Ogata; Yuuri Sugihara; Hidetoshi Onodera (FPL, 2006)

A 90nm 8×16 FPGA Enhancing Speed and Yield Utilizing Within-Die Variations. - Yuuri Sugihara; Manabu Kotani; Kazuya Katsuki; Kazutoshi Kobayashi; Hidetoshi Onodera (ASP-DAC, 2007)

A 90 nm 48 x 48 LUT-Based FPGA Enhancing Speed and Yield Utilizing Within-Die Delay Variations. - Kazutoshi Kobayashi; Kazuya Katsuki; Manabu Kotani; Yuuri Sugihara; Yohei Kume; Hidetoshi Onodera (IEICE Trans. Electron., 2007)

Speed and yield enhancement by track swapping on critical paths utilizing random variations for FPGAs. - Yuuri Sugihara; Yohei Kume; Kazutoshi Kobayashi; Hidetoshi Onodera (FPGA, 2008)

A variation-aware constant-order optimization scheme utilizing delay detectors to search for fastest paths on FPGAS. - Kazutoshi Kobayashi; Yohei Kume; Cam Lai Ngo; Yuuri Sugihara; Hidetoshi Onodera (FPL, 2008)

Performance optimization by track swapping on critical paths utilizing random variations for FPGAS. - Yuuri Sugihara; Yohei Kume; Kazutoshi Kobayashi; Hidetoshi Onodera (FPL, 2008)