A 0.6-Tbps, 16-port SRAM design with 2-stage- pipeline and multi-stage-sensing scheme. - Koh Johguchi; Yuya Mukuda; Shinya Izumi; Hans Jürgen Mattausch; Tetsushi Koide (ESSCIRC, 2007)

A 2-stage-pipelined 16 port SRAM with 590Gbps random access bandwidth and large noise margin. - Koh Johguchi; Yuya Mukuda; Ken-ichi Aoyama; Hans Jürgen Mattausch; Tetsushi Koide (IEICE Electron. Express, 2007)