Graph Minors from Simulated Annealing for Annealing Machines with Sparse Connectivity. - Yuya Sugie; Yuki Yoshida; Normann Mertig; Takashi Takemoto; Hiroshi Teramoto; Atsuyoshi Nakamura; Ichigaku Takigawa; Shin-ichi Minato; Masanao Yamaoka; Tamiki Komatsuzaki (TPNC, 2018)

Minor-embedding heuristics for large-scale annealing processors with sparse hardware graphs of up to 102, 400 nodes. - Yuya Sugie; Yuki Yoshida; Normann Mertig; Takashi Takemoto; Hiroshi Teramoto; Atsuyoshi Nakamura; Ichigaku Takigawa; Shin-ichi Minato; Masanao Yamaoka; Tamiki Komatsuzaki (Soft Comput., 2021)