Graph-Learning-Driven Path-Based Timing Analysis Results Predictor from Graph-Based Timing Analysis. - Yuyang Ye 001; Tinghuan Chen; Yifei Gao; Hao Yan 002; Bei Yu 001; Longxing Shi (ASP-DAC, 2023)

Fast and Accurate Wire Timing Estimation Based on Graph Learning. - Yuyang Ye 001; Tinghuan Chen; Yifei Gao; Hao Yan 002; Bei Yu 001; Longxing Shi (DATE, 2023)

FPGNN-ATPG: An Efficient Fault Parallel Automatic Test Pattern Generator. - Yuyang Ye 001; Zonghui Wang; Zun Xue; Ziqi Wang; Yifei Gao; Hao Yan 002 (ACM Great Lakes Symposium on VLSI, 2023)

Optimized matrix ordering of sparse linear solver using a few-shot model for circuit simulation. - Qian Chen; Yuyang Ye 001; Meng Li; Hao Yan 002; Longxing Shi (Integr., 2023)

Aging-Aware Critical Path Selection via Graph Attention Networks. - Yuyang Ye 001; Tinghuan Chen; Yifei Gao; Hao Yan 002; Bei Yu 001; Longxing Shi (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2023)

Heterogeneous Graph Attention Network Based Statistical Timing Library Characterization with Parasitic RC Reduction. - Xu Cheng; Yuyang Ye 001; Guoqing He; Qianqian Song; Peng Cao 002 (ASPDAC, 2024)

An Optimization-aware Pre-Routing Timing Prediction Framework Based on Heterogeneous Graph Learning. - Guoqing He; Wenjie Ding; Yuyang Ye 001; Xu Cheng; Qianqian Song; Peng Cao 002 (ASPDAC, 2024)

ARS-Flow: A Design Space Exploration Flow for Accelerator-rich System based on Active Learning. - Shuaibo Huang; Yuyang Ye 001; Hao Yan 002; Longxing Shi (ASPDAC, 2024)

A Graph-Learning-Driven Prediction Method for Combined Electromigration and Thermomigration Stress on Multi-Segment Interconnects. - Yunfan Zuo; Yuyang Ye 001; Hongchao Zhang; Tinghuan Chen; Hao Yan 002; Longxing Shi (DATE, 2024)

RankTuner: When Design Tool Parameter Tuning Meets Preference Bayesian Optimization. - Peng Xu; Su Zheng; Yuyang Ye 001; Chen Bai; Siyuan Xu; Hao Geng; Tsung-Yi Ho; Bei Yu 001 (ICCAD, 2024)

Fast and Accurate Aging-Aware Cell Timing Model via Graph Learning. - Yuyang Ye 001; Tinghuan Chen; Zicheng Wang; Hao Yan 002; Bei Yu 001; Longxing Shi (IEEE Trans. Circuits Syst. II Express Briefs, 2024)

Timing-Driven Technology Mapping Approximation Based on Reinforcement Learning. - Yuyang Ye 001; Tinghuan Chen; Yifei Gao; Hao Yan 002; Bei Yu 001; Longxing Shi (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2024)

Timing-Driven Approximate Logic Synthesis Based on Double-Chase Grey Wolf Optimizer. - Xiangfei Hu; Yuyang Ye 001; Tinghuan Chen; Hao Yan 002; Bei Yu 001 (DATE, 2025)

GraphCAD: Leveraging Graph Neural Networks for Accuracy Prediction Handling Crosstalk-affected Delays. - Fangzhou Liu; Guannan Guo; Yuyang Ye 001; Ziyi Wang 010; Wenjie Fu 003; Weihua Sheng; Bei Yu 001 (ISPD, 2025)

ARS-Flow 2.0: An enhanced design space exploration flow for accelerator-rich system based on active learning. - Shuaibo Huang; Yuyang Ye 001; Hao Yan 002; Longxing Shi (Integr., 2025)

A Hybrid Domain and Pipelined Analog Computing Chain for MVM Computation. - Tianzhu Xiong; Yuyang Ye 001; Xin Si; Jun Yang 006 (IEEE Trans. Very Large Scale Integr. Syst., 2025)

Learning-Driven Physically Aware Large-Scale Circuit Gate Sizing. - Yuyang Ye 001; Peng Xu; Lizheng Ren; Tinghuan Chen; Hao Yan 002; Bei Yu 001; Longxing Shi (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2025)