In-memory Processing based on Time-domain Circuit. - Yuyao Kong; Jun Yang 006 (ACM Great Lakes Symposium on VLSI, 2019)

Sandwich-RAM: An Energy-Efficient In-Memory BWN Architecture with Pulse-Width Modulation. - Jun Yang 006; Yuyao Kong; Zhen Wang 019; Yan Liu; Bo Wang 023; Shouyi Yin; Longxin Shi (ISSCC, 2019)

A Time-Domain Computing-in-Memory based Processor using Predictable Decomposed Convolution for Arbitrary Quantized DNNs. - Jianxun Yang; Yuyao Kong; Zhao Zhang; Zhuangzhi Liu; Jing Zhou; Yiqi Wang 005; Yonggang Liu; Chenfu Guo; Te Hu; Congcong Li; Leibo Liu; Jin Zhang; et al. (A-SSCC, 2020)

Design Methodology towards High-Precision SRAM based Computation-in-Memory for AI Edge Devices. - Tianzhu Xiong; Yongliang Zhou; Yuyao Kong; Bo Wang 023; An Guo 001; Yufei Wang; Chen Xue; Haiming Hsu; Xin Si; Jun Yang 006 (ISOCC, 2021)

Design Challenges and Methodology of High-Performance SRAM-Based Compute-in-Memory for AI Edge Devices. - Yufei Wang; Yongliang Zhou; Bo Wang 023; Tianzhu Xiong; Yuyao Kong; Xin Si (UCET, 2021)

TIMAQ: A Time-Domain Computing-in-Memory-Based Processor Using Predictable Decomposed Convolution for Arbitrary Quantized DNNs. - Jianxun Yang; Yuyao Kong; Zhao Zhang; Zhuangzhi Liu; Jing Zhou; Yiqi Wang 005; Yonggang Liu; Chenfu Guo; Te Hu; Congcong Li; Leibo Liu; Jin Zhang; et al. (IEEE J. Solid State Circuits, 2021)

SNNIM: A 10T-SRAM based Spiking-Neural-Network-In-Memory architecture with capacitance computation. - Bo Wang 023; Chen Xue; Han Liu; Xiang Li; Anran Yin; Zhongyuan Feng; Yuyao Kong; Tianzhu Xiong; Haiming Hsu; Yongliang Zhou; An Guo 001; Yufei Wang; et al. (ISCAS, 2022)

A 28nm 64-kb 31.6-TFLOPS/W Digital-Domain Floating-Point-Computing-Unit and Double-Bit 6T-SRAM Computing-in-Memory Macro for Floating-Point CNNs. - An Guo 001; Xin Si; Xi Chen 107; Fangyuan Dong; Xingyu Pu; Dongqi Li; Yongliang Zhou; Lizheng Ren; Yeyang Xue; Xueshan Dong; Hui Gao; Yiran Zhang; et al. (ISSCC, 2023)

A 28nm Horizontal-Weight-Shift and Vertical-feature-Shift-Based Separate-WL 6T-SRAM Computation-in-Memory Unit-Macro for Edge Depthwise Neural-Networks. - Bo Wang 023; Chen Xue; Zhongyuan Feng; Zhaoyang Zhang; Han Liu; Lizheng Ren; Xiang Li; Anran Yin; Tianzhu Xiong; Yeyang Xue; Shengnan He; Yuyao Kong; et al. (ISSCC, 2023)

Evaluation Platform of Time-Domain Computing-in-Memory Circuits. - Yuyao Kong; Xi Chen 107; Xin Si; Jun Yang 006 (IEEE Trans. Circuits Syst. II Express Briefs, 2023)

From macro to microarchitecture: reviews and trends of SRAM-based compute-in-memory circuits. - Zhaoyang Zhang; Jinwu Chen; Xi Chen 107; An Guo 001; Bo Wang 023; Tianzhu Xiong; Yuyao Kong; Xingyu Pu; Shengnan He; Xin Si; Jun Yang 006 (Sci. China Inf. Sci., 2023)

Toggle Rate Aware Quantization Model Based on Digital Floating-Point Computing-In-Memory Architecture. - Xi Chen 107; Yitong Zhao; An Guo 001; Jinwu Chen; Fangyuan Dong; Zhaoyang Zhang; Tianzhu Xiong; Bo Wang 023; Yuyao Kong; Xin Si (IEEE Trans. Circuits Syst. II Express Briefs, 2024)

Hardware Acceleration of Kolmogorov-Arnold Network (KAN) for Lightweight Edge Inference. - Wei-Hsing Huang; Jianwei Jia; Yuyao Kong; Faaiq G. Waqar; Tai-Hao Wen; Meng-Fan Chang; Shimeng Yu (ASP-DAC, 2025)

Digital Compute-in-Memory Ising Annealer with Ferroelectric Capacitor-Based nvSRAM for Combinatorial Optimization Problems. - Yuyao Kong; Jianwei Jia; Anni Lu; Faaiq G. Waqar; Yuan-Chun Luo; Hai Li 001; Ian A. Young; Shimeng Yu (ISCAS, 2025)

3DGauCIM: Accelerating Static/Dynamic 3D Gaussian Splatting via Digital CIM for High Frame Rate Real-Time Edge Rendering. - Wei-Hsing Huang; Cheng-Jhih Shih; Jian-Wei Su; Samuel Wade Wang; Vaidehi Garg; Yuyao Kong; Jen-Chun Tien; Nealson Li; Arijit Raychowdhury; Meng-Fan Chang; Yingyan Lin; Shimeng Yu (CoRR, 2025)

A3D-MoE: Acceleration of Large Language Models with Mixture of Experts via 3D Heterogeneous Integration. - Wei-Hsing Huang; Janak Sharda; Cheng-Jhih Shih; Yuyao Kong; Faaiq Waqar; Pin-Jun Chen; Yingyan Lin; Shimeng Yu (CoRR, 2025)