Fault Coverage Analysis for Physically-Based CMOS Bridging Faults at Different Power Supply Voltages. - Yuyun Liao; D. M. H. Walker (ITC, 1996)

The Palindrome network for fault-tolerant interconnection. - Yuyun Liao; Mi Lu; Nian-Feng Tzeng (SPDP, 1996)

Optimal voltage testing for physically-based faults. - Yuyun Liao; D. M. H. Walker (VTS, 1996)

An embedded 32-b microprocessor core for low-power and high-performance applications. - Lawrence T. Clark; Eric J. Hoffman; Jay B. Miller; Manish Biyani; Yuyun Liao; Stephen J. Strazdus; Michael Morrow; Kimberley E. Velarde; Mark A. Yarch (IEEE J. Solid State Circuits, 2001)

A high-performance and low-power 32-bit multiply-accumulate unit with single-instruction-multiple-data (SIMD) feature. - Yuyun Liao; David B. Roberts (IEEE J. Solid State Circuits, 2002)

An energy-efficient graphics processor featuring fine-grain DVFS with integrated voltage regulators, execution-unit turbo, and retentive sleep in 14nm tri-gate CMOS. - Pascal Meinerzhagen; Carlos Tokunaga; Andres Malavasi; Vaibhav A. Vaidya; Ashwin Mendon; Deepak Mathaikutty; Jaydeep Kulkarni; Charles Augustine; Minki Cho; Stephen T. Kim; George E. Matthew; Rinkle Jain; et al. (ISSCC, 2018)

Loihi: A Neuromorphic Manycore Processor with On-Chip Learning. - Mike Davies 002; Narayan Srinivasa; Tsung-Han Lin; Gautham N. Chinya; Yongqiang Cao; Sri Harsha Choday; Georgios D. Dimou; Prasad Joshi; Nabil Imam; Shweta Jain 005; Yuyun Liao; Chit-Kwan Lin; et al. (IEEE Micro, 2018)

An Energy-Efficient Graphics Processor in 14-nm Tri-Gate CMOS Featuring Integrated Voltage Regulators for Fine-Grain DVFS, Retentive Sleep, and ${V}_{ text{MIN}}$ Optimization. - Pascal Andreas Meinerzhagen; Carlos Tokunaga; Andres Malavasi; Vaibhav A. Vaidya; Ashwin Mendon; Deepak Mathaikutty; Jaydeep Kulkarni; Charles Augustine; Minki Cho; Stephen T. Kim; George E. Matthew; Rinkle Jain; et al. (IEEE J. Solid State Circuits, 2019)