Test generation for scan design circuits with tri-state modules and bidirectional terminals. - Takuji Ogihara; Shinichi Murai; Yuzo Takamatsu; Kozo Kinoshita; Hideo Fujiwara (DAC, 1983)

Test research in Japan. - Hideo Fujiwara; Yuzo Takamatsu; Takashi Nanya; Teruhiko Yamada; Hideo Tamamoto; Kiyoshi Furuya (IEEE Des. Test, 1988)

CONT: a concurrent test generation system. - Yuzo Takamatsu; Kozo Kinoshita (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1989)

Exponetiation in Finite Fields Using Dual Basis Multiplier. - Masakatu Morii; Yuzo Takamatsu (AAECC, 1990)

Extended selection of switching target faults in CONT algorithm for test generation. - Yuzo Takamatsu; Kozo Kinoshita (J. Electron. Test., 1990)

Generation of tenacious tests for small gate delay faults in combinational circuits. - Hiroshi Takahashi; Takashi Watanabe; Yuzo Takamatsu (Asian Test Symposium, 1995)

Enhancing multiple fault diagnosis in combinational circuits based on sensitized paths and EB testing. - Hiroshi Takahashi; Nobuhiro Yanagida; Yuzo Takamatsu (Asian Test Symposium, 1995)

Multiple Fault Diagnosis by Sensitizing Input Pairs. - Nobuhiro Yanagida; Hiroshi Takahashi; Yuzo Takamatsu (IEEE Des. Test Comput., 1995)

A Study for Testability of Redundant Faults in Combinational Circuits Using Delay Effects. - Xiangqiu Yu; Hiroshi Takahashi; Yuzo Takamatsu (IEICE Trans. Inf. Syst., 1995)

Test generation for sequential circuits using parallel fault simulation with random inputs. - Yuzo Takamatsu; Isao Higashi; Tsuyoshi Kodama (Syst. Comput. Jpn., 1995)

Multiple fault diagnosis in combinational circuits using sensitizing input-pairs. - Nobuhiro Yanagida; Hiroshi Takahashi; Yuzo Takamatsu (Syst. Comput. Jpn., 1995)

Multiple Fault Diagnosis in Sequential Circuits Using Sensitizing Sequence Pairs. - Nobuhiro Yanagida; Hiroshi Takahashi; Yuzo Takamatsu (FTCS, 1996)

Design of C-Testable Multipliers Based on the Modified Booth Algorithm. - Kwame Osei Boateng; Hiroshi Takahashi; Yuzo Takamatsu (Asian Test Symposium, 1997)

A Method of Generating Tests for Marginal Delays an Delay Faults in Combinational Circuits. - Hiroshi Takahashi; Kwame Osei Boateng; Yuzo Takamatsu; Toshiyuki Matsunaga (Asian Test Symposium, 1997)

Tests for small gate delay faults in combinational circuits and a test generation method. - Hiroshi Takahashi; Takashi Watanabe; Toshiyuki Matsunaga; Yuzo Takamatsu (Syst. Comput. Jpn., 1997)

Diagnosis of Single Gate Delay Faults in Combinational Circuits using Delay Fault Simulation. - Hiroshi Takahashi; Kwame Osei Boateng; Yuzo Takamatsu (Asian Test Symposium, 1998)

Electron Beam Tester Aided Fault Diagnosis for Logic Circuits Based on Sensitized Paths. - Nobuhiro Yanagida; Hiroshi Takahashi; Yuzo Takamatsu (Asian Test Symposium, 1998)

Fault Simulation Techniques to Reduce IDDQ Measurement Vectors for Sequential Circuits. - Yoshinobu Higami; Yuzo Takamatsu; Kewal K. Saluja; Kozo Kinoshita (Asian Test Symposium, 1999)

Multiple Fault Diagnosis in Logic Circuits Using EB Tester and Multiple/Single Fault Simulators. - Hiroshi Takahashi; Kwame Osei Boateng; Yuzo Takamatsu; Nobuhiro Yanagida (Asian Test Symposium, 1999)

A New Method for Diagnosing Multiple Stuck-at Faults using Multiple and Single Fault Simulations. - Hiroshi Takahashi; Kwame Osei Boateng; Yuzo Takamatsu (VTS, 1999)

Fault models and test generation for IDDQ testing: embedded tutorial. - Yoshinobu Higami; Yuzo Takamatsu; Kewal K. Saluja; Kozo Kinoshita (ASP-DAC, 2000)

Test sequence compaction for sequential circuits with reset states. - Yoshinobu Higami; Yuzo Takamatsu; Kozo Kinoshita (Asian Test Symposium, 2000)

General BIST-Amenable Method of Test Generation for Iterative Logic Arrays. - Kwame Osei Boateng; Hiroshi Takahashi; Yuzo Takamatsu (VTS, 2000)

Algorithms to Select IDDQ Measurement Vectors for Bridging Faults in Sequential Circuits. - Yoshinobu Higami; Yuzo Takamatsu; Kewal K. Saluja; Kozo Kinoshita (J. Electron. Test., 2000)

Static test compaction for IDDQ testing of bridging faults in sequential circuits. - Yoshinobu Higami; Kewal K. Saluja; Yuzo Takamatsu; Kozo Kinoshita (Syst. Comput. Jpn., 2000)

Identification of redundant faults in combinational circuits. - Tetsuro Minamiyama; Yuzo Takamatsu (Syst. Comput. Jpn., 2000)

Test Generation for Double Stuck-at Faults. - Yoshinobu Higami; Naoko Takahashi; Yuzo Takamatsu (Asian Test Symposium, 2001)

Simulation-Based Diagnosis for Crosstalk Faults in Sequential Circuits. - Hiroshi Takahashi; Marong Phadoongsidhi; Yoshinobu Higami; Kewal K. Saluja; Yuzo Takamatsu (Asian Test Symposium, 2001)

On reducing the target fault list of crosstalk-induced delay faults in synchronous sequential circuits. - Keith J. Keller; Hiroshi Takahashi; Kewal K. Saluja; Yuzo Takamatsu (ITC, 2001)

A Method to Reduce Power Dissipation during Test for Sequential Circuits. - Yoshinobu Higami; Shin-ya Kobayashi; Yuzo Takamatsu (Asian Test Symposium, 2002)

Reduction of Target Fault List for Crosstalk-Induced Delay Faults by using Layout Constraints. - Keith J. Keller; Hiroshi Takahashi; Kim T. Le; Kewal K. Saluja; Yuzo Takamatsu (Asian Test Symposium, 2002)

Modifying Test Vectors for Reducing Power Dissipation in CMOS Circuits. - Yoshinobu Higami; Shin-ya Kobayashi; Yuzo Takamatsu (DELTA, 2002)

An Alternative Method of Generating Tests for Path Delay Faults Using N -Detection Test Sets. - Hiroshi Takahashi; Kewal K. Saluja; Yuzo Takamatsu (PRDC, 2002)

On diagnosing multiple stuck-at faults using multiple and singlefault simulation in combinational circuits. - Hiroshi Takahashi; Kwame Osei Boateng; Kewal K. Saluja; Yuzo Takamatsu (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2002)

BIST Based Fault Diagnosis Using Ambiguous Test Set. - Hiroshi Takahashi; Yasunori Tsugaoka; Hidekazu Ayano; Yuzo Takamatsu (DFT, 2003)

A Method to Find Don't Care Values in Test Sequences for Sequential Circuits. - Yoshinobu Higami; Shin-ya Kobayashi; Yuzo Takamatsu; Seiji Kajihara; Irith Pomeranz (ICCD, 2003)

Techniques for Finding Xs in Test Sequences for Sequential Circuits and Applications to Test Length/Power Reduction. - Yoshinobu Higami; Seiji Kajihara; Shin-ya Kobayashi; Yuzo Takamatsu (Asian Test Symposium, 2004)

Failure Analysis of Open Faults by Using Detecting/Un-detecting Information on Tests. - Yuichi Sato; Hiroshi Takahashi; Yoshinobu Higami; Yuzo Takamatsu (Asian Test Symposium, 2004)

Enhancing BIST Based Single/Multiple Stuck-at Fault Diagnosis by Ambiguous Test Set. - Hiroshi Takahashi; Yukihiro Yamamoto; Yoshinobu Higami; Yuzo Takamatsu (Asian Test Symposium, 2004)

Generation of Test Sequences with Low Power Dissipation for Sequential Circuits. - Yoshinobu Higami; Shin-ya Kobayashi; Yuzo Takamatsu (IEICE Trans. Inf. Syst., 2004)

On the fault diagnosis in the presence of unknown fault models using pass/fail information. - T. Seiyama; Hiroshi Takahashi; Yoshinobu Higami; Kazuo Yamazaki; Yuzo Takamatsu (ISCAS (3), 2005)

Test cost reduction for logic circuits: Reduction of test data volume and test application time. - Yoshinobu Higami; Seiji Kajihara; Hideyuki Ichihara; Yuzo Takamatsu (Syst. Comput. Jpn., 2005)

A method for reducing the target fault list of crosstalk faults in synchronous sequential circuits. - Hiroshi Takahashi; Keith J. Keller; Kim T. Le; Kewal K. Saluja; Yuzo Takamatsu (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2005)

Compaction of pass/fail-based diagnostic test vectors for combinational and sequential circuits. - Yoshinobu Higami; Kewal K. Saluja; Hiroshi Takahashi; Shin-ya Kobayashi; Yuzo Takamatsu (ASP-DAC, 2006)

Diagnosis of Transistor Shorts in Logic Test Environment. - Yoshinobu Higami; Kewal K. Saluja; Hiroshi Takahashi; Sin-ya Kobayashi; Yuzo Takamatsu (ATS, 2006)

Fanout-based fault diagnosis for open faults on pass/fail information. - Koji Yamazaki; Yuzo Takamatsu (ATS, 2006)

Effective Post-BIST Fault Diagnosis for Multiple Faults. - Hiroshi Takahashi; Shuhei Kadoyama; Yoshinobu Higami; Yuzo Takamatsu; Koji Yamazaki; Takashi Aikyo; Yasuo Sato (DFT, 2006)

On Finding Don't Cares in Test Sequences for Sequential Circuits. - Yoshinobu Higami; Seiji Kajihara; Irith Pomeranz; Shin-ya Kobayashi; Yuzo Takamatsu (IEICE Trans. Inf. Syst., 2006)

Test Generation for Transistor Shorts using Stuck-at Fault Simulator and Test Generator. - Yoshinobu Higami; Kewal K. Saluja; Hiroshi Takahashi; Shin-ya Kobayashi; Yuzo Takamatsu (ATS, 2007)

Clues for Modeling and Diagnosing Open Faults with Considering Adjacent Lines. - Hiroshi Takahashi; Yoshinobu Higami; Shuhei Kadoyama; Takashi Aikyo; Yuzo Takamatsu; Koji Yamazaki; Toshiyuki Tsutsumi; Hiroyuki Yotsuyanagi; Masaki Hashizume (ATS, 2007)

Timing-Aware Diagnosis for Small Delay Defects. - Takashi Aikyo; Hiroshi Takahashi; Yoshinobu Higami; Junichi Ootsu; Kyohei Ono; Yuzo Takamatsu (DFT, 2007)

Test Generation and Diagnostic Test Generation for Open Faults with Considering Adjacent Lines. - Hiroshi Takahashi; Yoshinobu Higami; Toru Kikkawa; Takashi Aikyo; Yuzo Takamatsu; Hiroyuki Yotsuyanagi; Masaki Hashizume (DFT, 2007)

Fault Coverage and Fault Efficiency of Transistor Shorts using Gate-Level Simulation and Test Generation. - Yoshinobu Higami; Kewal K. Saluja; Hiroshi Takahashi; Yuzo Takamatsu (VLSI Design, 2007)

Increasing Defect Coverage by Generating Test Vectors for Stuck-Open Faults. - Yoshinobu Higami; Kewal K. Saluja; Hiroshi Takahashi; Shin-ya Kobayashi; Yuzo Takamatsu (ATS, 2008)

Fault Simulation and Test Generation for Transistor Shorts Using Stuck-at Test Tools. - Yoshinobu Higami; Kewal K. Saluja; Hiroshi Takahashi; Shin-ya Kobayashi; Yuzo Takamatsu (IEICE Trans. Inf. Syst., 2008)

Maximizing Stuck-Open Fault Coverage Using Stuck-at Test Vectors. - Yoshinobu Higami; Kewal K. Saluja; Hiroshi Takahashi; Shin-ya Kobayashi; Yuzo Takamatsu (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2008)

Post-BIST Fault Diagnosis for Multiple Faults. - Hiroshi Takahashi; Yoshinobu Higami; Shuhei Kadoyama; Yuzo Takamatsu; Koji Yamazaki; Takashi Aikyo; Yasuo Sato (IEICE Trans. Inf. Syst., 2008)

Fault Diagnosis on Multiple Fault Models by Using Pass/Fail Information. - Yuzo Takamatsu; Hiroshi Takahashi; Yoshinobu Higami; Takashi Aikyo; Koji Yamazaki (IEICE Trans. Inf. Syst., 2008)

A Method of Locating Open Faults on Incompletely Identified Pass/Fail Information. - Koji Yamazaki; Yuzo Takamatsu (IEICE Trans. Inf. Syst., 2008)

New Class of Tests for Open Faults with Considering Adjacent Lines. - Hiroshi Takahashi; Yoshinobu Higami; Yuzo Takamatsu; Koji Yamazaki; Toshiyuki Tsutsumi; Hiroyuki Yotsuyanagi; Masaki Hashizume (Asian Test Symposium, 2009)

Diagnostic test generation for transition faults using a stuck-at ATPG tool. - Yoshinobu Higami; Yosuke Kurose; Satoshi Ohno; Hironori Yamaoka; Hiroshi Takahashi; Yoshihiro Shimizu; Takashi Aikyo; Yuzo Takamatsu (ITC, 2009)

A Novel Approach for Improving the Quality of Open Fault Diagnosis. - Koji Yamazaki; Toshiyuki Tsutsumi; Hiroshi Takahashi; Yoshinobu Higami; Takashi Aikyo; Yuzo Takamatsu; Hiroyuki Yotsuyanagi; Masaki Hashizume (VLSI Design, 2009)

Fault Effect of Open Faults Considering Adjacent Signal Lines in a 90 nm IC. - Hiroyuki Yotsuyanagi; Masaki Hashizume; Toshiyuki Tsutsumi; Koji Yamazaki; Takashi Aikyo; Yoshinobu Higami; Hiroshi Takahashi; Yuzo Takamatsu (VLSI Design, 2009)

Addressing Defect Coverage through Generating Test Vectors for Transistor Defects. - Yoshinobu Higami; Kewal K. Saluja; Hiroshi Takahashi; Shin-ya Kobayashi; Yuzo Takamatsu (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2009)

An Algorithm for Diagnosing Transistor Shorts Using Gate-level Simulation. - Yoshinobu Higami; Kewal K. Saluja; Hiroshi Takahashi; Sin-ya Kobayashi; Yuzo Takamatsu (Inf. Media Technol., 2009)

An Algorithm for Diagnosing Transistor Shorts Using Gate-level Simulation. - Yoshinobu Higami; Kewal K. Saluja; Hiroshi Takahashi; Shin-ya Kobayashi; Yuzo Takamatsu (IPSJ Trans. Syst. LSI Des. Methodol., 2009)