Reconfigurable 2T2R ReRAM with Split Word-Lines for TCAM Operation and In-Memory Computing. - Yuzong Chen 001; Lu Lu 013; Bongjin Kim; Tony Tae-Hyoung Kim (ISCAS, 2020)

Reconfigurable 2T2R ReRAM Architecture for Versatile Data Storage and Computing In-Memory. - Yuzong Chen 001; Lu Lu 013; Bongjin Kim; Tony Tae-Hyoung Kim (IEEE Trans. Very Large Scale Integr. Syst., 2020)

A Multi-Functional 4T2R ReRAM Macro Enabling 2-Dimensional Access and Computing In-Memory. - Yuzong Chen 001; Lu Lu 013; Yuncheng Lu; Tony Tae-Hyoung Kim (ISCAS, 2021)

A Configurable Randomness Enhanced RRAM PUF with Biased Current Sensing Scheme. - Lu Lu 013; Yuzong Chen 001; Tony Tae-Hyoung Kim (ISCAS, 2021)

AND8T SRAM Macro with Improved Linearity for Multi-Bit In-Memory Computing. - Vishal Sharma 004; Ju Eon Kim; Yong-Jun Jo; Yuzong Chen 001; Tony Tae-Hyoung Kim (ISCAS, 2021)

A Reconfigurable 4T2R ReRAM Computing In-Memory Macro for Efficient Edge Applications. - Yuzong Chen 001; Lu Lu 013; Bongjin Kim; Tony Tae-Hyoung Kim (IEEE Open J. Circuits Syst., 2021)

A 181µW Real-Time 3-D Hand Gesture Recognition System based on Bi-directional Convolution and Computing-Efficient Feature Clustering. - Yuncheng Lu; Zehao Li; Yuzong Chen 001; Tony Tae-Hyoung Kim (CICC, 2022)

A Reconfigurable 8T SRAM Macro for Bit-Parallel Searching and Computing In-Memory. - Yuzong Chen 001; Junjie Mu; Hyunjoon Kim; Lu Lu 013; Tony Tae-Hyoung Kim (ISCAS, 2022)

An Overview of Processing-in-Memory Circuits for Artificial Intelligence and Machine Learning. - Donghyuk Kim; Chengshuo Yu; Shanshan Xie; Yuzong Chen 001; Joo-Young Kim 001; Bongjin Kim; Jaydeep P. Kulkarni; Tony Tae-Hyoung Kim (IEEE J. Emerg. Sel. Topics Circuits Syst., 2022)

BRAMAC: Compute-in-BRAM Architectures for Multiply-Accumulate on FPGAs. - Yuzong Chen 001; Mohamed S. Abdelfattah (FCCM, 2023)

M4BRAM: Mixed-Precision Matrix-Matrix Multiplication in FPGA Block RAMs. - Yuzong Chen 001; Jordan Dotzel; Mohamed S. Abdelfattah (ICFPT, 2023)

BP-SCIM: A Reconfigurable 8T SRAM Macro for Bit-Parallel Searching and Computing In-Memory. - Yuzong Chen 001; Junjie Mu; Hyunjoon Kim; Lu Lu 013; Tony Tae-Hyoung Kim (IEEE Trans. Circuits Syst. I Regul. Pap., 2023)

FPGA Benchmark for Unrolled DNNs with Fine-Grained Sparsity and Mixed Precision. - Xilai Dai; Yuzong Chen 001; Mohamed S. Abdelfattah (FCCM, 2024)

Kratos: An FPGA Benchmark for Unrolled DNNs with Fine-Grained Sparsity and Mixed Precision. - Xilai Dai; Yuzong Chen 001; Mohamed S. Abdelfattah (FPL, 2024)

Learning from Students: Applying t-Distributions to Explore Accurate and Efficient Formats for LLMs. - Jordan Dotzel; Yuzong Chen 001; Bahaa Kotb; Sushma Prasad; Gang Wu; Sheng Li 007; Mohamed S. Abdelfattah; Zhiru Zhang (ICML, 2024)

BBS: Bi-Directional Bit-Level Sparsity for Deep Learning Acceleration. - Yuzong Chen 001; Jian Meng; Jae-sun Seo; Mohamed S. Abdelfattah (MICRO, 2024)

BitMoD: Bit-serial Mixture-of-Datatype LLM Acceleration. - Yuzong Chen 001; Ahmed F. AbouElhamayed; Xilai Dai; Yang Wang; Marta Andronic; George A. Constantinides; Mohamed S. Abdelfattah (HPCA, 2025)

The Power of Negative Zero: Datatype Customization for Quantized Large Language Models. - Yuzong Chen 001; Xilai Dai; Chi-chih Chang; Yash Akhauri; Mohamed S. Abdelfattah (CoRR, 2025)