Formal Verification of CHP Specifications with CADP Illustration on an Asynchronous Network-on-Chip. - Gwen Salaün; Wendelin Serwe; Yvain Thonnart; Pascal Vivet (ASYNC, 2007)

ASC, a SystemC Extension for Modeling Asynchronous Systems, and Its Application to an Asynchronous NoC. - Cedric Koch-Hofer; Marc Renaudin; Yvain Thonnart; Pascal Vivet (NOCS, 2007)

Implementation of a Design-for-Test Architecture for Asynchronous Networks-on-Chip. - Xuan-Tu Tran; Jean Durupt; Yvain Thonnart; François Bertrand; Vincent Beroulle; Chantal Robach (NOCS, 2007)

Automatic Power Regulation Based on an Asynchronous Activity Detection and its Application to ANOC Node Leakage Reduction. - Yvain Thonnart; Edith Beigné; Alexandre Valentian; Pascal Vivet (ASYNC, 2008)

Quantitative Evaluation in Embedded System Design: Validation of Multiprocessor Multithreaded Architectures. - Nicolas Coste; Hubert Garavel; Holger Hermanns; Richard Hersemeule; Yvain Thonnart; Meriem Zidouni (DATE, 2008)

A Design-for-Test Implementation of an Asynchronous Network-on-Chip Architecture and its Associated Test Pattern Generation and Application. - Xuan-Tu Tran; Yvain Thonnart; Jean Durupt; Vincent Beroulle; Chantal Robach (NOCS, 2008)

Design and Implementation of a GALS Adapter for ANoC Based Architectures. - Yvain Thonnart; Edith Beigné; Pascal Vivet (ASYNC, 2009)

An Open and Reconfigurable Platform for 4G Telecommunication: Concepts and Application. - Fabien Clermidy; Romain Lemaire; Xavier Popon; Dimitri Ktenas; Yvain Thonnart (DSD, 2009)

A Communication and configuration controller for NoC based reconfigurable data flow architecture. - Fabien Clermidy; Romain Lemaire; Yvain Thonnart; Pascal Vivet (NOCS, 2009)

Design-for-test approach of an asynchronous network-on-chip architecture and its associated test pattern generation and application. - Xuan-Tu Tran; Yvain Thonnart; Jean Durupt; Vincent Beroulle; Chantal Robach (IET Comput. Digit. Tech., 2009)

An Asynchronous Power Aware and Adaptive NoC Based Circuit. - Edith Beigné; Fabien Clermidy; Hélène Lhermet; Sylvain Miermont; Yvain Thonnart; Xuan-Tu Tran; Alexandre Valentian; Didier Varreau; Pascal Vivet; Xavier Popon; Hugo Lebreton (IEEE J. Solid State Circuits, 2009)

Power Reduction of Asynchronous Logic Circuits Using Activity Detection. - Yvain Thonnart; Edith Beigné; Alexandre Valentian; Pascal Vivet (IEEE Trans. Very Large Scale Integr. Syst., 2009)

An analytical method for evaluating Network-on-Chip performance. - Sahar Foroutan; Yvain Thonnart; Richard Hersemeule; Ahmed Jerraya (DATE, 2010)

A fully-asynchronous low-power framework for GALS NoC integration. - Yvain Thonnart; Pascal Vivet; Fabien Clermidy (DATE, 2010)

A Markov chain based method for NoC end-to-end latency evaluation. - Sahar Foroutan; Yvain Thonnart; Richard Hersemeule; Ahmed Jerraya (IPDPS Workshops, 2010)

A 477mW NoC-based digital baseband for MIMO 4G SDR. - Fabien Clermidy; Christian Bernard; Romain Lemaire; Jérôme Martin; Ivan Miro Panades; Yvain Thonnart; Pascal Vivet; Norbert Wehn (ISSCC, 2010)

Distributed Sequencing for Resource Sharing in Multi-applicative Heterogeneous NoC Platforms. - Yvain Thonnart; Romain Lemaire; Fabien Clermidy (NOCS, 2010)

3D NoC using through silicon Via: An asynchronous implementation. - Pascal Vivet; Denis Dutoit; Yvain Thonnart; Fabien Clermidy (VLSI-SoC, 2011)

A Pseudo-Synchronous Implementation Flow for WCHB QDI Asynchronous Circuits. - Yvain Thonnart; Edith Beigné; Pascal Vivet (ASYNC, 2012)

Ultra-wide voltage range designs in fully-depleted silicon-on-insulator FETs. - Edith Beigné; Alexandre Valentian; Bastien Giraud; Olivier Thomas; Thomas Benoist; Yvain Thonnart; Serge Bernard; Guillaume Moritz; Olivier Billoint; Y. Maneglia; Philippe Flatresse; Jean-Philippe Noel; et al. (DATE, 2013)

A fine grain variation-aware dynamic Vdd-hopping AVFS architecture on a 32nm GALS MPSoC. - Edith Beigné; Ivan Miro-Panades; Yvain Thonnart; Laurent Alacoque; Pascal Vivet; Suzanne Lesecq; Diego Puschini; Farhat Thabet; Benoît Tain; K. Benchehida; Sylvain Engels; Robin Wilson; et al. (ESSCIRC, 2013)

Fine grain multi-VT co-integration methodology in UTBB FD-SOI technology. - Bertrand Pelloux-Prayer; Alexandre Valentian; Bastien Giraud; Yvain Thonnart; Jean-Philippe Noel; Philippe Flatresse; Edith Beigné (VLSI-SoC, 2013)

An Iterative Computational Technique for Performance Evaluation of Networks-on-Chip. - Sahar Foroutan; Yvain Thonnart; Frédéric Pétrot (IEEE Trans. Computers, 2013)

27.1 A 460MHz at 397mV, 2.6GHz at 1.3V, 32b VLIW DSP, embedding FMAX tracking. - Robin Wilson; Edith Beigné; Philippe Flatresse; Alexandre Valentian; Fady Abouzeid; Thomas Benoist; Christian Bernard; Sebastien Bernard; Olivier Billoint; Sylvain Clerc; Bastien Giraud; Anuj Grover; et al. (ISSCC, 2014)

Technology assessment of silicon interposers for manycore SoCs: Active, passive, or optical? - Yvain Thonnart; Mounir Zid (NOCS, 2014)

Introduction to the special session on "Silicon photonic interconnects: an illusion or a realistic solution?". - Jiang Xu 001; Sébastien Le Beux; Yvain Thonnart (NOCS, 2014)

A Fine-Grain Variation-Aware Dynamic Vdd-Hopping AVFS Architecture on a 32 nm GALS MPSoC. - Ivan Miro Panades; Edith Beigné; Yvain Thonnart; Laurent Alacoque; Pascal Vivet; Suzanne Lesecq; Diego Puschini; Anca Molnos; Farhat Thabet; Benoît Tain; Karim Ben Chehida; Sylvain Engels; et al. (IEEE J. Solid State Circuits, 2014)

3D advanced integration technology for heterogeneous systems. - Pascal Vivet; Christian Bernard; Fabien Clermidy; Denis Dutoit; Eric Guthmuller; Ivan Miro Panades; Gaël Pillonnet; Yvain Thonnart; Arnaud Garnier; Didier Lattard; Amandine Jouve; Franck Bana; et al. (3DIC, 2015)

Two-phase protocol converters for 3D asynchronous 1-of-n data links. - Julian J. H. Pontes; Pascal Vivet; Yvain Thonnart (ASP-DAC, 2015)

Complementary communication path for energy efficient on-chip optical interconnects. - Hui Li 034; Sébastien Le Beux; Yvain Thonnart; Ian O'Connor (DAC, 2015)

Coherent crosstalk noise analyses in ring-based optical interconnects. - Luan H. K. Duong; Mahdi Nikdast; Jiang Xu 001; Zhehui Wang; Yvain Thonnart; Sébastien Le Beux; Peng Yang 003; Xiaowen Wu; Zhifei Wang (DATE, 2015)

Fine-grain DVFS and AVFS techniques for complex SoC design: An overview of architectural solutions through technology nodes. - Edith Beigné; Fabien Clermidy; Didier Lattard; Ivan Miro Panades; Yvain Thonnart; Pascal Vivet (ISCAS, 2015)

Interconnect Challenges for 3D Multi-cores: From 3D Network-on-Chip to Cache Interconnects. - Pascal Vivet; Christian Bernard; Eric Guthmuller; Ivan Miro Panades; Yvain Thonnart; Fabien Clermidy (ISVLSI, 2015)

A 460 MHz at 397 mV, 2.6 GHz at 1.3 V, 32 bits VLIW DSP Embedding F MAX Tracking. - Edith Beigné; Alexandre Valentian; Ivan Miro Panades; Robin Wilson; Philippe Flatresse; Fady Abouzeid; Thomas Benoist; Christian Bernard; Sebastien Bernard; Olivier Billoint; Sylvain Clerc; Bastien Giraud; et al. (IEEE J. Solid State Circuits, 2015)

8.1 A 4×4×2 homogeneous scalable 3D network-on-chip circuit with 326MFlit/s 0.66pJ/b robust and fault-tolerant asynchronous 3D links. - Pascal Vivet; Yvain Thonnart; Romain Lemaire; Edith Beigné; Christian Bernard; Florian Darve; Didier Lattard; Ivan Miro Panades; Cristiano Santos; Fabien Clermidy; Séverine Cheramy; Frédéric Pétrot; et al. (ISSCC, 2016)

10 Gbps, 560 fJ/b TIA and modulator driver for optical networks-on-chip in CMOS 65nm. - Jose-Luis Gonzalez Jimenez; Robert Polster; Guillaume Waltener; Yvain Thonnart; Eric Cassan (NEWCAS, 2016)

Coherent and Incoherent Crosstalk Noise Analyses in Interchip/Intrachip Optical Interconnection Networks. - Luan H. K. Duong; Zhehui Wang; Mahdi Nikdast; Jiang Xu 001; Peng Yang 003; Zhifei Wang; Zhe Wang 003; Rafael K. V. Maeda; Haoran Li 002; Xuan Wang 001; Sébastien Le Beux; Yvain Thonnart (IEEE Trans. Very Large Scale Integr. Syst., 2016)

Efficiency Optimization of Silicon Photonic Links in 65-nm CMOS and 28-nm FDSOI Technology Nodes. - Robert Polster; Yvain Thonnart; Guillaume Waltener; Jose-Luis Gonzalez Jimenez; Eric Cassan (IEEE Trans. Very Large Scale Integr. Syst., 2016)

In-situ Fmax/Vmin tracking for energy efficiency and reliability optimization. - Ivan Miro Panades; Edith Beigné; Olivier Billoint; Yvain Thonnart (IOLTS, 2017)

A 4 × 4 × 2 Homogeneous Scalable 3D Network-on-Chip Circuit With 326 MFlit/s 0.66 pJ/b Robust and Fault Tolerant Asynchronous 3D Links. - Pascal Vivet; Yvain Thonnart; Romain Lemaire; Cristiano Santos; Edith Beigné; Christian Bernard; Florian Darve; Didier Lattard; Ivan Miro Panades; Denis Dutoit; Fabien Clermidy; Séverine Cheramy; et al. (IEEE J. Solid State Circuits, 2017)

A 10Gb/s Si-photonic transceiver with 150μW 120μs-lock-time digitally supervised analog microring wavelength stabilization for 1Tb/s/mm2 Die-to-Die Optical Networks. - Yvain Thonnart; Mounir Zid; Jose-Luis Gonzalez Jimenez; Guillaume Waltener; Robert Polster; Olivier Dubray; Florent Lepin; Stéphane Bernabé; Sylvie Menezo; Gabriel Pares; Olivier Castany; Laura Boutafa; et al. (ISSCC, 2018)

Latency Improvement of an Industrial SoC System Interconnect using an Asynchronous NoC Backbone. - Yvain Thonnart; Pascal Vivet; Shikhanshu Agarwal; Ramesh Chauhan (ASYNC, 2019)

WAVES: Wavelength Selection for Power-Efficient 2.5D-Integrated Photonic NoCs. - Aditya Narayan; Yvain Thonnart; Pascal Vivet; César Fuguet Tortolero; Ayse K. Coskun (DATE, 2019)

System-level Evaluation of Chip-Scale Silicon Photonic Networks for Emerging Data-Intensive Applications. - Aditya Narayan; Yvain Thonnart; Pascal Vivet; Ajay Joshi; Ayse K. Coskun (DATE, 2020)

POPSTAR: a Robust Modular Optical NoC Architecture for Chiplet-based 3D Integrated Systems. - Yvain Thonnart; Stéphane Bernabé; Jean Charbonnier; Christian Bernard; David Coriat; César Fuguet Tortolero; Pierre Tissier; Benoît Charbonnier; Stéphane Malhouitre; Damien Saint-Patrice; Myriam Assous; Aditya Narayan; et al. (DATE, 2020)

19.2 A 110mK 295µW 28nm FDSOI CMOS Quantum Integrated Circuit with a 2.8GHz Excitation and nA Current Sensing of an On-Chip Double Quantum Dot. - Loïck Le Guevel; Gérard Billiot; Xavier Jehl; Silvano De Franceschi; Marcos Zurita; Yvain Thonnart; Maud Vinet; Marc Sanquer; Romain Maurand; Aloysius G. M. Jansen; Gaël Pillonnet (ISSCC, 2020)

2.3 A 220GOPS 96-Core Processor with 6 Chiplets 3D-Stacked on an Active Interposer Offering 0.6ns/mm Latency, 3Tb/s/mm2 Inter-Chiplet Interconnects and 156mW/mm2@ 82%-Peak-Efficiency DC-DC Converters. - Pascal Vivet; Eric Guthmuller; Yvain Thonnart; Gaël Pillonnet; Guillaume Moritz; Ivan Miro-Panades; César Fuguet Tortolero; Jean Durupt; Christian Bernard; Didier Varreau; Julian J. H. Pontes; Sébastien Thuries; et al. (ISSCC, 2020)

SE2: Going Remote: Challenges and Opportunities to Remote Learning, Work, and Collaboration. - Alicia Klinefelter; Huichu Liu; Luca Benini; Yvain Thonnart; Keith A. Bowman; Kathy Wilcox; David Bol; Alvin Loke; Ofer Shacham (ISSCC, 2021)

Designing a Multi-Chiplet Manycore System using the POPSTAR Optical NoC Architecture (Invited). - Yvain Thonnart (SLIP, 2021)

IntAct: A 96-Core Processor With Six Chiplets 3D-Stacked on an Active Interposer With Distributed Interconnects and Integrated Power Management. - Pascal Vivet; Eric Guthmuller; Yvain Thonnart; Gaël Pillonnet; César Fuguet Tortolero; Ivan Miro-Panades; Guillaume Moritz; Jean Durupt; Christian Bernard; Didier Varreau; Julian J. H. Pontes; Sébastien Thuries; et al. (IEEE J. Solid State Circuits, 2021)

PROWAVES: Proactive Runtime Wavelength Selection for Energy-Efficient Photonic NoCs. - Aditya Narayan; Yvain Thonnart; Pascal Vivet; Ayse K. Coskun (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2021)

Architecting Optically Controlled Phase Change Memory. - Aditya Narayan; Yvain Thonnart; Pascal Vivet; Ayse K. Coskun; Ajay Joshi (ACM Trans. Archit. Code Optim., 2022)

A Cryogenic Active Router for Qubit Array Biasing from DC to 320 MHz at 100 nm Gate Pitch. - Baptiste Jadot; Marcos Zurita; Gérard Billiot; Yvain Thonnart; Loïck Le Guevel; Mathieu Darnas; Candice Thomas; Jean Charbonnier; Tristan Meunier; Maud Vinet; Franck Badets; Gaël Pillonnet (ESSCIRC, 2023)

Benefits of Design Assist Techniques on Performances and Reliability of a RRAM Macro. - Bastien Giraud; Sebastien Ricavy; Yasser Moursy; Cyrille Laffond; Ilan Sever; Valentin Gherman; Manuel Pezzin; Florent Lepin; Mariam Diallo; Khadija Zenati; Sylvain Dumas; Maxim Vershkov; et al. (IMW, 2023)

SamurAI: A Versatile IoT Node With Event-Driven Wake-Up and Embedded ML Acceleration. - Ivan Miro-Panades; Benoît Tain; Jean-Frédéric Christmann; David Coriat; Romain Lemaire; Clement Jany; Baudouin Martineau; Fabrice Chaix; Guillaume Waltener; Emmanuel Pluchart; Jean-Philippe Noel; Adam Makosiej; et al. (IEEE J. Solid State Circuits, 2023)

A 7.4μW and 860μm2per Channel Cryo-CMOS IC for 70-Channel Frequency-Multiplexed μs-Readout of Semiconductor Qubits. - Quentin Schmidt; Brian Martinez; Thomas Houriez; Baptiste Jadot; Aloysius G. M. Jansen; Xavier Jehl; Tristan Meunier; Gaël Pillonnet; Gérard Billiot; Adrien Morel; Yvain Thonnart; Franck Badets (CICC, 2024)

Smart Write Algorithm to Enhance Performances and Reliability of an RRAM Macro. - Bastien Giraud; Sebastien Ricavy; Cyrille Laffond; Ilan Sever; Valentin Gherman; Florent Lepin; Mariam Diallo; Khadija Zenati; Sylvain Dumas; Olivier Guille; Maxim Vershkov; Alessandro Bricalli; et al. (IEEE J. Solid State Circuits, 2024)

Cryogenic Circuit Performance Prediction Using Design-Oriented Model (SEKV) On 22nm FDSOI. - Brian Martinez; Hung-Chi Han; Flávio Enrico Bergamaschi; Quentin Schmidt; Antoine Faurie; Edoardo Charbon; Yvain Thonnart; Baptiste Jadot; Xavier Jehl; Mikaël Cassé; Christian C. Enz; Franck Badets (ISCAS, 2025)

13.5 An 18.5µW/qubit Cryo-CMOS Charge-Readout IC Demonstrating QAM Multiplexing for Spin Qubits. - Quentin Schmidt; Baptiste Jadot; Brian Martinez; Antoine Faurie; Tristan Meunier; Jean-Baptiste Casanova; Xavier Jehl; Yvain Thonnart; Franck Badets (ISSCC, 2025)