Optimization of Motion Estimator for Run-Time-Reconfiguration Implementation. - Camel Tanougast; Yves Berviller; Serge Weber (IPDPS Workshops, 2000)

Automated RTR Temporal Partitioning for Reconfigurable Embedded Real-Time System Design. - Camel Tanougast; Yves Berviller; Philippe Brunet; Serge Weber (IPDPS, 2003)

Hardware Partitioning Software for Dynamically Reconfigurable SoC Design. - Philippe Brunet; Camel Tanougast; Yves Berviller; Serge Weber (IWSOC, 2003)

A Partitioning Methodology That Optimises the Area on Reconfigurable Real-Time Embedded Systems. - Camel Tanougast; Yves Berviller; Serge Weber; Philippe Brunet (EURASIP J. Adv. Signal Process., 2003)

Temporal partitioning methodology optimizing FPGA resources for dynamically reconfigurable embedded real-time system. - Camel Tanougast; Yves Berviller; Philippe Brunet; Serge Weber; Hassan Rabah (Microprocess. Microsystems, 2003)

FPGA Implementation of a Novel Architecture for PCR Related Measurements In DVB-T. - Christian Mannino; Hassan Rabah; Camel Tanougast; Yves Berviller; Michael Janiaut; Serge Weber (ESA/VLSI, 2004)

FPGA Implementation of a Novel All Digital PLL Architecture for PCR Related Measurements in DVB-T. - Christian Mannino; Hassan Rabah; Camel Tanougast; Yves Berviller; Michael Janiaut; Serge Weber (FPL, 2004)

SystemC Model of a MPEG-2 DVB-T Bit-Rate Measurement Architecture for FPGA Implementation. - Camel Tanougast; Yves Berviller; Christian Mannino; Hassan Rabah; Michael Janiaut; Serge Weber (IEEE International Workshop on Rapid System Prototyping, 2004)

Configurable hardware implementation of a conceptual decoder for a real-time MPEG-2 analysis. - Michael Janiaut; Camel Tanougast; Hassan Rabah; Yves Berviller; Christian Mannino; Serge Weber (FPL, 2005)

A Design Methodology for Power Electronics Digital Control based on an FPGA in the Loop Prototyping. - Shahram Karimi; Philippe Poure; Yves Berviller; Shahrokh Saadate (ICECS, 2007)

The Use of Runtime Reconfiguration on FPGA Circuits to Increase the Performance of the AES Algorithm Implementation. - Oscar Pérez; Yves Berviller; Camel Tanougast; Serge Weber (J. Univers. Comput. Sci., 2007)

FPGA-based SoC for transcoding H264/AVC-SVC with low latency and high bitrate entropy coding. - Michael Guarisco; Hassan Rabah; Yves Berviller; Serge Weber; Said Belkouch (SoCC, 2009)

An Embedded and Programmable System Based FPGA for Real Time MPEG Stream Buffer Analysis. - Camel Tanougast; Michael Janiaut; Yves Berviller; Hassan Rabah; Serge Weber; Ahmed Bouridane (IEEE Trans. Circuits Syst. Video Technol., 2009)

FPGA-based architectures of finite radon transform for medical image de-noising. - Afandi Ahmad; Abbes Amira; Hassan Rabah; Yves Berviller (APCCAS, 2010)

Efficient implementation of a 3-D medical imaging compression system using CAVLC. - Afandi Ahmad; Abbes Amira; Michael Guarisco; Hassan Rabah; Yves Berviller (ICIP, 2010)

An efficient VLSI implementation of H.264/AVC intra-frame transcoder. - Michael Guarisco; Eric Dabellani; Nicolas Marques; Hassan Rabah; Yves Berviller; Serge Weber (ICECS, 2011)

Medical image denoising on field programmable gate array using finite Radon transform. - Afandi Ahmad; Abbes Amira; Hassan Rabah; Yves Berviller (IET Signal Process., 2012)

Modeling and FPGA implementation of reconfigurable transcoder for real time video adaptation. - Eric Dabellani; Hassan Rabah; Nicolas Marques; Yves Berviller; Slavisa Jovanovic; Serge Weber (ICECS, 2013)

Contextual Detection of Pedestrians and Vehicles in Orthophotography by Fusion of Deep Learning Algorithms. - Masoomeh Shireen Ansarnia; Etienne Tisserand; Patrick Schweitzer; Mohamed Amine Zidane; Yves Berviller (Sensors, 2022)

Road User Position and Speed Estimation via Deep Learning from Calibrated Fisheye Videos. - Yves Berviller; Masoomeh Shireen Ansarnia; Etienne Tisserand; Patrick Schweitzer; Alain Trémeau (Sensors, 2023)