VHDL design of a priority interrupt controller and synchronizer for the MC68008. - Yves Blaquière; Jacob Davidson (Microprocess. Microsystems, 1990)

Cost analysis of a new algorithmic-based soft-error tolerant architecture. - Yves Blaquière; Gabriel Gagné; Yvon Savaria; Claude Évéquoz (DFT, 1995)

Timing analysis speed-up using a hierarchical and a multimode approach. - Yves Blaquière; Michel R. Dagenais; Yvon Savaria (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1996)

A Comparative Analysis of Fuzzy ART Neural Network Implementations: The Advantages of Reconfigurable Computing. - Pascal Poiré; Marc-André Cantin; Hervé Daniel; Yves Blaquière; Yvon Savaria (FCCM, 1998)

Analysis of quantization effects in a digital hardware implementation of a fuzzy ART neural network algorithm. - Marc-André Cantin; Yves Blaquière; Yvon Savaria; Pierre Lavoie; Eric Granger (ISCAS, 2000)

Digital Measurement Technique for Capacitance Variation Detection on Integrated Circuit I/Os. - Yves Blaquière; Yvon Savaria; Jaouad El Fouladi (ICECS, 2007)

Hardware/software system co-verification of an active reconfigurable board with SystemC-VHDL. - Yan Basile-Bellavance; Etienne Lepercq; Yves Blaquière; Yvon Savaria (ICECS, 2008)

Digital signal propagation on a wafer-scale smart active programmable interconnect. - Olivier Valorge; Anh Tuan Nguyen; Yves Blaquière; Richard Norman; Yvon Savaria (ICECS, 2008)

Workflow for an Electronic Configurable Prototyping System. - Etienne Lepercq; Yves Blaquière; Richard Norman; Yvon Savaria (ISCAS, 2009)

Thermo-mechanical analysis of a reconfigurable wafer-scale integrated circuit. - Mohammed Bougataya; Oussama Berriah; Ahmed Lakhssassi; Adel-Omar Dahmane; Yves Blaquière; Yvon Savaria; Richard Norman; Richard Prytula (ICECS, 2010)

A spatially reconfigurable fast differential interface for a wafer scale configurable platform. - Olivier Valorge; Yves Blaquière; Yvon Savaria (ICECS, 2010)

A large range and fine tuning configurable Bandgap reference dedicated to wafer-scale systems. - Nicolas Laflamme-Mayer; Yves Blaquière; Mohamad Sawan (ICECS, 2011)

Machine-learning framework for automatic netlist creation. - Mohamed Badreddine; Yves Blaquière; Mounir Boukadoum (ISCAS, 2011)

Propagating analog signals through a fully digital network on an electronic system prototyping platform. - Omar Al-Terkawi Hasib; Walder Andre; Yves Blaquière; Yvon Savaria (ISCAS, 2012)

SoC systems thermal monitoring using embedded sensor cells unit. - Michel Sayde; Ahmed Lakhssassi; Mohammed Bougataya; Omar Terkawi; Yves Blaquière (MWSCAS, 2012)

A new approach for pin detection for an electronic system prototyping reconfigurable platform. - Hai H. Nguyen; Mikael Guillemot; Yvon Savaria; Yves Blaquière (RSP, 2012)

Software rendering methods to display wafer scale integrated circuit dataset. - Mikael Guillemot; Yves Blaquière; Yvon Savaria (CCECE, 2013)

An interface for the I2C protocol in the WaferBoard™. - Wasim Hussain; Yvon Savaria; Yves Blaquière (ISCAS, 2013)

A configurable analog buffer dedicated to a wafer-scale prototyping platform of electronic systems. - Nicolas Laflamme-Mayer; Mohamad Sawan; Yves Blaquière (LASCAS, 2013)

A netlist pruning tool for an electronic system prototyping platform. - Karim Baratli; Ahmed Lakhssassi; Yves Blaquière; Yvon Savaria (NEWCAS, 2013)

Configurable Input-Output Power Pad for Wafer-Scale Microelectronic Systems. - Nicolas Laflamme-Mayer; Walder Andre; Olivier Valorge; Yves Blaquière; Mohamad Sawan (IEEE Trans. Very Large Scale Integr. Syst., 2013)

Design and validation of a novel reconfigurable and defect tolerant JTAG scan chain. - Yves Blaquière; Yan Basile-Bellavance; Safa Berrima; Yvon Savaria (ISCAS, 2014)

A Configurable Multi-Rail Power and I/O Pad Applied to Wafer-Scale Systems. - Nicolas Laflamme-Mayer; Yves Blaquière; Yvon Savaria; Mohamad Sawan (IEEE Trans. Circuits Syst. I Regul. Pap., 2014)

An automated fault injection for evaluation of LUTs robustness in SRAM-based FPGAs. - Anis Souari; Claude Thibeault; Yves Blaquière; Raoul Velazco (EWDTS, 2015)

Defect diagnosis algorithms for a field programmable interconnect network embedded in a Very Large Area Integrated Circuit. - Gontran Sion; Yves Blaquière; Yvon Savaria (IOLTS, 2015)

Optimization of SEU emulation on SRAM FPGAs based on sensitiveness analysis. - Anis Souari; Claude Thibeault; Yves Blaquière; Raoul Velazco (IOLTS, 2015)

Circuit Level Modeling of Extra Combinational Delays in SRAM FPGAs Due to Transient Ionizing Radiation. - Mostafa Darvishi; Yves Audet; Yves Blaquière; Claude Thibeault (CoRR, 2015)

An Interface for Open-Drain Bidirectional Communication in Field Programmable Interconnection Networks. - Wasim Hussain; Yves Blaquière; Yvon Savaria (IEEE Trans. Circuits Syst. I Regul. Pap., 2015)

A compact spatially configurable differential input stage for a field programmable interconnection network. - Wasim Hussain; Yvon Savaria; Yves Blaquière (ISCAS, 2016)

A novel spatially configurable differential interface for an electronic system prototyping platform. - Wasim Hussain; Olivier Valorge; Yves Blaquière; Yvon Savaria (Integr., 2016)

Towards an efficient SEU effects emulation on SRAM-based FPGAs. - Anis Souari; Claude Thibeault; Yves Blaquière; Raoul Velazco (Microelectron. Reliab., 2016)

An Asynchronous Delta-Modulator Based A/D Converter for an Electronic System Prototyping Platform. - Wasim Hussain; Hussein Fakhoury; Patricia Desgreys; Yves Blaquière; Yvon Savaria (IEEE Trans. Circuits Syst. I Regul. Pap., 2016)

A multi-measurements RO-TDC implemented in a Xilinx field programmable gate array. - Safa Berrima; Yves Blaquière; Yvon Savaria (ISCAS, 2017)

Sub-ps resolution programmable delays implemented in a Xilinx FPGA. - Safa Berrima; Yves Blaquière; Yvon Savaria (MWSCAS, 2017)

Delay Monitor Circuit for Sensitive Nodes in SRAM-Based FPGA. - Mostafa Darvishi; Yves Audet; Yves Blaquière (CoRR, 2018)

Diagnosis algorithms for a reconfigurable and defect tolerant JTAG scan chain in large area integrated circuits. - Safa Berrima; Yves Blaquière; Yvon Savaria (Integr., 2018)

A pattern-based routing algorithm for a novel electronic system prototyping platform. - Etienne Lepercq; Yves Blaquière; Yvon Savaria (Integr., 2018)

Toward In-System Monitoring of OpenCL-Based Designs on FPGA. - Hachem Bensalem; Yves Blaquière; Yvon Savaria (ISCAS, 2019)

A Defect-Tolerant Reusable Network of DACs for Wafer-Scale Integration. - Nicolas Laflamme-Mayer; Gilbert Kowarzyk; Yves Blaquière; Yvon Savaria; Mohamad Sawan (IEEE Trans. Very Large Scale Integr. Syst., 2019)

A High Voltage Multi-Purpose On-the-fly Reconfigurable Half-Bridge Gate Driver for GaN HEMTs in 0.18-μm HV SOI CMOS Technology. - Nam Ly; Nueraimaiti Aimaier; Abdul Hafiz Alameh; Yves Blaquière; Glenn E. R. Cowan; Nicolas G. Constantin (NEWCAS, 2020)

In-FPGA Instrumentation Framework for OpenCL-Based Designs. - Hachem Bensalem; Yves Blaquière; Yvon Savaria (IEEE Access, 2020)

Fine resolution delay tuning method to improve the linearity of an unbalanced time-to-digital converter on a Xilinx FPGA. - Safa Berrima; Yves Blaquière; Yvon Savaria (IET Circuits Devices Syst., 2020)

SHEPWM Class-D Amplifier with a Reconfigurable Gate Driver Integrated Circuit. - Nueraimaiti Aimaier; Nam Ly; Gabriel Nobert; Yves Blaquière; Nicolas G. Constantin; Glenn E. R. Cowan (ISCAS, 2021)

Acceleration of the Secure Hash Algorithm-256 (SHA-256) on an FPGA-CPU Cluster Using OpenCL. - Hachem Bensalem; Yves Blaquière; Yvon Savaria (ISCAS, 2021)

A Novel Minimum-Phase Dual-Inductor Hybrid Boost Converter with PWM Voltage-Mode Controller. - Van Ha Nguyen; Abdul Hafiz Alameh; Nam Ly; Yves Blaquière; Glenn E. R. Cowan (ISCAS, 2021)

Compact and Low-Power Under-Voltage Lockout and Thermal-Shutdown Protection Circuits Using a Novel Low-Iq All-in-One Bandgap Comparator. - Van Ha Nguyen; Nam Ly; Abdul Hafiz Alameh; Yves Blaquière; Glenn E. R. Cowan (ISCAS, 2021)

Towards an LTCC SiP for Control System in Safety-Critical Applications. - Gabriel Nobert; Abdul Hafiz Alameh; Nam Ly; Nicolas G. Constantin; Yves Blaquière (ISCAS, 2021)

A Versatile 200-V Capacitor-Coupled Level Shifter for Fully Floating Multi-MHz Gate Drivers. - Van Ha Nguyen; Nam Ly; Abdul Hafiz Alameh; Yves Blaquière; Glenn E. R. Cowan (IEEE Trans. Circuits Syst. II Express Briefs, 2021)

Ring-Oscillator-Based High Accuracy Low Complexity Multichannel Time-to-Digital Converter Architecture for Field-Programmable Gate Arrays. - Safa Berrima; Yves Blaquière; Yvon Savaria (IEEE Trans. Instrum. Meas., 2021)

A Reconfigurable Power System-in-Package Module using GaN HEMTs and IC Bare Dies on LTCC Substrate: Design - Implementation - Experiment and Future Directions. - Van Ha Nguyen; Nueraimaiti Aimaier; Gabriel Nobert; Tan Pham; Nicolas G. Constantin; Yves Blaquière; Glenn E. R. Cowan (NEWCAS, 2022)

Multi-Phase Hybrid Boost Converter with High Conduction Loss Reduction and Fast Dynamic Response for Automotive Applications. - Van Ha Nguyen; Xuan-Dien Do; Yves Blaquière; Glenn E. R. Cowan (NEWCAS, 2022)

A 3.3 V 0.1-1 A Hybrid Buck-Boost Converter with 85-97 % Power Efficiency Range Highly-Suited for Battery-Powered Devices using Low-Profile High-DCR Inductor. - Van Ha Nguyen; Xuan-Dien Do; Yves Blaquière; Glenn E. R. Cowan (NEWCAS, 2022)

A MEMS Electrothermal Actuator Designed for a DC Switch Aimed at Power Switching Applications and High Voltage Resilience. - Abdurrashid Hassan Shuaibu; Frédéric Nabki; Yves Blaquière (NEWCAS, 2022)

Toward 2.5D Structures for Multi-Channel MEMS Acoustic-Based Digital Isolators using Through Silicon Openings. - Hamid Sadrimanesh; Yves Blaquière; Frederic Nabki (NEWCAS, 2023)

Toward a Polysilicon-Based Electrostatically Actuated DC MEMS Switch. - Abdurrashid Hassan Shuaibu; Yves Blaquière; Frédéric Nabki (NEWCAS, 2023)

An Efficient OpenCL-Based Implementation of a SHA-3 Co-Processor on an FPGA-Centric Platform. - Hachem Bensalem; Yves Blaquière; Yvon Savaria (IEEE Trans. Circuits Syst. II Express Briefs, 2023)

A Precise and Reliable Engine Knock Detection Utilizing Meta Classifier. - Amirhossein Moshrefi; Yves Blaquière; Frederic Nabki (ISCAS, 2024)

Configurable and Intelligent Switched CMOS Current Driver Powering Arrays of Electrothermal Actuators for MEMS Switches. - Allan Riboullet; Frédéric Nabki; Yves Blaquière; Glenn E. R. Cowan (ISCAS, 2024)

Hybrid Graph Representation and Learning Framework for High-Level Synthesis Design Space Exploration. - Pouya Taghipour; Eric Granger; Yves Blaquière (IEEE Access, 2024)