Expériences en synthèse logique. (Experiments in logic synthesis). - Yves Durand (1988)

A Middleware Architecture for Personalized Communities of Devices. - Gavin Brebner; Yves Durand; Stéphane Perret (DCW, 2002)

Radiometric and geometric correction of RADARSAT-1 images acquired in alpine regions for mapping the snow water equivalent (SWE). - Jean-Pierre Dedieu; Yves Gauthier; Monique Bernier; Stéphane Hardy; Pierre Vincent; Yves Durand (IGARSS, 2003)

Performance Evaluation of a NoC-Based Design for MC-CDMA Telecommunications Using NS-2. - Romain Lemaire; Fabien Clermidy; Yves Durand; Didier Lattard; Ahmed Amine Jerraya (IEEE International Workshop on Rapid System Prototyping, 2005)

Power Modeling of a NoC Based Design for High Speed Telecommunication Systems. - Philippe Grosse; Yves Durand; Paul Feautrier (PATMOS, 2006)

A Telecom Baseband Circuit based on an Asynchronous Network-on-Chip. - Didier Lattard; Edith Beigné; Christian Bernard; Catherine Bour; Fabien Clermidy; Yves Durand; Jean Durupt; Didier Varreau; Pascal Vivet; Pierre Penard; Arnaud Bouttier; Friedbert Berens (ISSCC, 2007)

A Reconfigurable Baseband Platform Based on an Asynchronous Network-on-Chip. - Didier Lattard; Edith Beigné; Fabien Clermidy; Yves Durand; Romain Lemaire; Pascal Vivet; Friedbert Berens (IEEE J. Solid State Circuits, 2008)

A Microprogrammable Memory Controller for high-performance dataflow applications. - Jérôme Martin; Christian Bernard; Fabien Clermidy; Yves Durand (ESSCIRC, 2009)

The Radio Virtual Machine: A solution for SDR portability and platform reconfigurability. - Riadh Ben Abdallah; Tanguy Risset; Antoine Fraboulet; Yves Durand (IPDPS, 2009)

Snowpack Characterization in Mountainous Regions Using C-Band SAR Data and a Meteorological Model. - Nicolas Longépé; Sophie Allain; Laurent Ferro-Famil; Eric Pottier; Yves Durand (IEEE Trans. Geosci. Remote. Sens., 2009)

Methods for power optimization in SOC-based data flow systems. - Philippe Grosse; Yves Durand; Paul Feautrier (ACM Trans. Design Autom. Electr. Syst., 2009)

Multi-temporal wet snow mapping in alpine context using polarimetric Radarsat-2 time-series. - Audrey Lessard-Fontaine; Sophie Allain-Bailhache; Jean-Pierre Dedieu; Yves Durand (IGARSS, 2012)

Multilayer snowpack backscattering model and assimilation of TerraSAR-X satellite data. - Xuan-Vu Phan; Laurent Ferro-Famil; Michel Gay; Yves Durand; Marie Dumont; Guy D'Urso (IGARSS, 2012)

EUROSERVER: Energy Efficient Node for European Micro-Servers. - Yves Durand; Paul M. Carpenter; Stefano Adami; Angelos Bilas; Denis Dutoit; Alexis Farcy; Georgi Gaydadjiev; John Goodacre; Manolis Katevenis; Manolis Marazakis; Emil Matús; Iakovos Mavroidis; et al. (DSD, 2014)

Dry snow analysis in alpine regions using RADARSAT-2 full polarimetry data. Comparison with in situ measurements. - Jean-Pierre Dedieu; Nikola Besic; Gabriel Vasile; Julien Mathieu; Yves Durand; Frederic Gottardi (IGARSS, 2014)

Comparison between DMRT simulations for multilayer snowpack and data from NoSREx report. - Xuan-Vu Phan; Laurent Ferro-Famil; Michel Gay; Yves Durand; Marie Dumont (IGARSS, 2014)

Assimilation of TerraSAR-X data into a snowpack model. - Xuan-Vu Phan; Michel Gay; Laurent Ferro-Famil; Yves Durand; Marie Dumont (IGARSS, 2014)

Guaranteed Services of the NoC of a Manycore Processor. - Benoît Dupont de Dinechin; Yves Durand; Duco van Amstel; Alexandre Ghiti (NoCArc@MICRO, 2014)

EUROSERVER: Share-anything scale-out micro-server design. - Manolis Marazakis; John Goodacre; Didier Fuin; Paul M. Carpenter; John Thomson; Emil Matús; Antimo Bruno; Per Stenström; Jérôme Martin; Yves Durand; Isabelle Dor (DATE, 2016)

Distributed Dynamic Rate Adaptation on a Network on Chip with Traffic Distortion. - Yves Durand; Christian Bernard; Fabien Clermidy (MCSoC, 2016)

A methodology for the design of dynamic accuracy operators by runtime back bias. - Daniele Jahier Pagliari; Yves Durand; David Coriat; Anca Molnos; Edith Beigné; Enrico Macii; Massimo Poncino (DATE, 2017)

A Programmable Inbound Transfer Processor for Active Messages in Embedded Multicore Systems. - Yves Durand; Christian Bernard; Romain Lemaire; César Fuguet Tortolero; Emilie Garat (DSD, 2017)

Evaluation of approximate operators case study: sobel filter application executed on an approximate RISC-V platform. - Geneviève Ndour; Tiago Trevisan Jost; Anca Molnos; Yves Durand; Arnaud Tisserand (SAMOS, 2018)

Dynamic Precision Numerics Using a Variable-Precision UNUM Type I HW Coprocessor. - Andrea Bocco; Yves Durand; Florent de Dinechin (ARITH, 2019)

Error Analysis of the Square Root Operation for the Purpose of Precision Tuning: A Case Study on K-means. - Oumaima Matoussi; Yves Durand; Olivier Sentieys; Anca Molnos (ASAP, 2019)

Evaluation of variable bit-width units in a RISC-V processor for approximate computing. - Geneviève Ndour; Tiago Trevisan Jost; Anca Molnos; Yves Durand; Arnaud Tisserand (CF, 2019)

Byte-Aware Floating-point Operations through a UNUM Computing Unit. - Andrea Bocco; Tiago T. Jost; Albert Cohen 001; Florent de Dinechin; Yves Durand; Christian Fabre (VLSI-SoC, 2019)

Fine-Grain Back Biasing for the Design of Energy-Quality Scalable Operators. - Daniele Jahier Pagliari; Yves Durand; David Coriat; Edith Beigné; Enrico Macii; Massimo Poncino (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2019)

VP Float: First Class Treatment for Variable Precision Floating Point Arithmetic. - Tiago T. Jost; Yves Durand; Christian Fabre; Albert Cohen 001; Frédéric Pétrot (PACT, 2020)

Channel-bonding CMOS transceiver for 100 Gbps wireless point-to-point links. - José Luis González-Jiménez; Cédric Dehos; Nicolas Cassiau; Alexandre Siligaris; Antonio Clemente; Rafaelle D'Errico; Valentin Savin; Yves Durand; Antonio De Domenico; Dominique Noguet (EURASIP J. Wirel. Commun. Netw., 2020)

Seamless Compiler Integration of Variable Precision Floating-Point Arithmetic. - Tiago Trevisan Jost; Yves Durand; Christian Fabre; Albert Cohen 001; Frédéric Pétrot (CGO, 2021)

Accelerating Variants of the Conjugate Gradient with the Variable Precision Processor. - Yves Durand; Eric Guthmuller; César Fuguet Tortolero; Jérôme Fereyre; Andrea Bocco; Riccardo Alidori (ARITH, 2022)

SpDCache: Region-Based Reduction Cache for Outer-Product Sparse Matrix Kernels. - Valentin Isaac-Chassande; Adrian Evans; Yves Durand; Frédéric Rousseau 001 (ASAP, 2024)

A Variable and Extended Precision (VRP) Accelerator and its 22 nm SoC Implementation. - César Fuguet; Eric Guthmuller; Andrea Bocco; Jérôme Fereyre; Adrian Evans; Yves Durand (DCIS, 2024)

Stabilizing the Block BiCG with Extended Precision: A Case Study. - Alexandre Hoffmann; Yves Durand; Jérôme Fereyre (PPAM (1), 2024)

Dedicated Hardware Accelerators for Processing of Sparse Matrices and Vectors: A Survey. - Valentin Isaac-Chassande; Adrian Evans; Yves Durand; Frédéric Rousseau 001 (ACM Trans. Archit. Code Optim., 2024)

Xvpfloat: RISC-V ISA Extension for Variable Extended Precision Floating Point Computation. - Eric Guthmuller; César Fuguet; Andrea Bocco; Jérôme Fereyre; Riccardo Alidori; Ihsane Tahir; Yves Durand (IEEE Trans. Computers, 2024)