A Design for Machines with Built-In Tolerance to Soft Errors. - Yvon Savaria; Vinod K. Agarwal; Nicholas C. Rumin; Jeremiah F. Hayes (ITC, 1984)

A Theory for the Design of Soft-Error-Tolerant VLSI Circuits. - Yvon Savaria; Jeremiah F. Hayes; Nicholas C. Rumin; Vinod K. Agarwal (IEEE J. Sel. Areas Commun., 1986)

Soft-error filtering: A solution to the reliability problem of future VLSI digital circuits. - Yvon Savaria; Nicholas C. Rumin; Jeremiah F. Hayes; Vinold K. Agarwal (Proc. IEEE, 1986)

New architectures for fast convolutional encoders and threshold decoders. - David Haccoun; Pierre Lavoie; Yvon Savaria (IEEE J. Sel. Areas Commun., 1988)

Design-for-Testability Using Test Design Yield and Decision Theory. - Bozena Kaminska; Yvon Savaria (ITC, 1989)

A Pragmatic Approach to the Design of Self-Testing Circuits. - Yvon Savaria; Bruno Laguë; Bozena Kaminska (ITC, 1989)

New VLSI architectures for fast soft-decision threshold decoders. - Pierre Lavoie; David Haccoun; Yvon Savaria (IEEE Trans. Commun., 1991)

Test quality of hierarchical defect-tolerant integrated circuits. - Claude Thibeault; Yvon Savaria; Jean-Louis Houle (J. Electron. Test., 1992)

Heuristic Prediction of the Optimum Number of spares in Defect-Tolerant Integrated Circuits. - Claude Thibeault; Yvon Savaria; Jean-Louis Houle (J. Circuits Syst. Comput., 1992)

Performance improvements to VLSI parallel systems, using dynamic concatenation of processing resources. - Daniel Audet; Yvon Savaria; Jean-Louis Houle (Parallel Comput., 1992)

Some Results on Yield and Local Design Rule Relaxation. - J. Crépeau; Claude Thibeault; Yvon Savaria (DFT, 1993)

Initiability: A Measure of Sequential Testability. - Naim Ben-Hamida; Bozena Kaminska; Yvon Savaria (ISCAS, 1993)

A High Speed Parallel Structure for the Basic Wavelet Transform Algorithm. - Hakim Khali; Jean-Louis Houle; Yvon Savaria (ISCAS, 1993)

Parallel Regeneration of Interconnections in VLSI & ULSI Circuits. - Mohamed Nekili; Yvon Savaria (ISCAS, 1993)

Defect and Fault Tolerant Scan Chains. - Rachid Kermouche; Yvon Savaria (DFT, 1994)

Estimation of Simultaneous Switching Power and Ground Noise of Static CMOS Combinational Circuits. - Abdessatar Abderrahman; Bozena Kaminska; Yvon Savaria (EDAC-ETC-EUROASIC, 1994)

Fast Convergence with Low Precision Weights in ART1 Networks. - Jean-François Crespo; Pierre Lavoie; Yvon Savaria (ISCAS, 1994)

A Comparative Study of Single-Phase Clocked Latches Using Estimation Criteria. - Sameh Ghannoum; Dmitri Chtchvyrkov; Yvon Savaria (ISCAS, 1994)

Pseudo-Random Vector Compaction for Sequential Testability. - Naim Ben-Hamida; Bozena Kaminska; Yvon Savaria (ISCAS, 1994)

A Fast Low-Power Driver for Long Interconnections in VLSI Systems. - Mohamed Nekili; Yvon Savaria; Guy Bois (ISCAS, 1994)

A Fast CMOS Voltage-Controlled Ring Oscillator. - Yvon Savaria; Dmitri Chtchvyrkov; John F. Currie (ISCAS, 1994)

A Fast Method to Evaluate the Optimum Number of Spares in Defect-Tolerant Integrated Circuits. - Claude Thibeault; Yvon Savaria; Jean-Louis Houle (IEEE Trans. Computers, 1994)

A multiprocessor architecture for multiple path stack sequential decoders. - Normand Bélanger; David Haccoun; Yvon Savaria (IEEE Trans. Commun., 1994)

A systolic architecture for fast stack sequential decoders. - Pierre Lavoie; David Haccoun; Yvon Savaria (IEEE Trans. Commun., 1994)

Pipelining communications in large VLSI/ULSI systems. - Daniel Audet; Yvon Savaria; N. Arel (IEEE Trans. Very Large Scale Integr. Syst., 1994)

A new method for testing mixed analog and digital circuits. - Janusz Rzeszut; Bozena Kaminska; Yvon Savaria (Asian Test Symposium, 1995)

Cost analysis of a new algorithmic-based soft-error tolerant architecture. - Yves Blaquière; Gabriel Gagné; Yvon Savaria; Claude Évéquoz (DFT, 1995)

On Using Partial Reset for Pseudo-Random Testing. - Mohamed Soufi; Yvon Savaria; Bozena Kaminska (ISCAS, 1995)

On the design of at-speed testable VLSI circuits. - Mohamed Soufi; Yvon Savaria; Bozena Kaminska (VTS, 1995)

Producing Reliable Initialization and Test of Sequential Circuits with Pseudorandom Vectors. - Mohamed Soufi; Yvon Savaria; F. Darlay; Bozena Kaminska (IEEE Trans. Computers, 1995)

Equivalence Proofs of Some Yield Modeling Methods for Defect-Tolerant Integrated Circuits. - Claude Thibeault; Yvon Savaria; Jean-Louis Houle (IEEE Trans. Computers, 1995)

Bounds on the performance of partial selection networks. - Jean Belzile; Yvon Savaria; David Haccoun; Martin Chalifoux (IEEE Trans. Commun., 1995)

Implementing Fault Injection and Tolerance Mechanisms in Multiprocessor Systems. - Daniel Audet; N. Gagnon; Yvon Savaria (DFT, 1996)

Design and performance of CMOS TSPC cells for high speed pseudo random testing. - Mohamed Soufi; Steve Rochon; Yvon Savaria; Bozena Kaminska (VTS, 1996)

Panel Summaries. - Yervant Zorian; Tom Anderson; Yvon Savaria; Claude Thibeault; André Ivanov (IEEE Des. Test Comput., 1996)

Reconstruction method for jitter tolerant data acquisition system. - Adel Belhaouane; Yvon Savaria; Bozena Kaminska; Daniel Massicotte (J. Electron. Test., 1996)

Timing analysis speed-up using a hierarchical and a multimode approach. - Yves Blaquière; Michel R. Dagenais; Yvon Savaria (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1996)

Are defect-tolerant circuits with redundancy really cost-effective? Complete and realistic cost model. - Yves Gagnon; Yvon Savaria; Michel Meunier; Claude Thibeault (DFT, 1997)

A Cost Model for VLSI / MCM Systems. - Michel Kafrouni; Claude Thibeault; Yvon Savaria (DFT, 1997)

Multiple categorization using fuzzy ART. - Pierre Lavoie; Jean-François Crespo; Yvon Savaria (ICNN, 1997)

Pipelined H-trees for high-speed clocking of large integrated systems in presence of process variations. - Mohamed Nekili; Guy Bois; Yvon Savaria (IEEE Trans. Very Large Scale Integr. Syst., 1997)

Reducing Fault Sensitivity of Microprocessor-Based Systems by Modifying Workload Structure. - Daniel Audet; Steve Masson; Yvon Savaria (DFT, 1998)

A Comparative Analysis of Fuzzy ART Neural Network Implementations: The Advantages of Reconfigurable Computing. - Pascal Poiré; Marc-André Cantin; Hervé Daniel; Yves Blaquière; Yvon Savaria (FCCM, 1998)

Design of Clock Distribution Networks in Presence of Process Variations. - Mohamed Nekili; Yvon Savaria; Guy Bois (Great Lakes Symposium on VLSI, 1998)

Optimal design of synchronous circuits using software pipelining techniques. - François R. Boyer; El Mostapha Aboulhamid; Yvon Savaria; Imed Eddine Bennour (ICCD, 1998)

Parallel ultra large scale engine SIMD architecture for real-time digital signal processing applications. - Paul Marriott; Ivan C. Kraljic; Yvon Savaria (ICCD, 1998)

A comparison of self-organizing neural networks for fast clustering of radar pulses. - Eric Granger; Yvon Savaria; Pierre Lavoie; Marc-André Cantin (Signal Process., 1998)

Design For Testability Method for CML Digital Circuits. - Bernard Antaki; Yvon Savaria; Nanhan Xiong; Saman Adham (DATE, 1999)

Design of a JTAG Based Run Time Reconfigurable System. - Cynthia Cousineau; François Laperle; Yvon Savaria (FCCM, 1999)

Jitter model of direct digital synthesis clock generators. - Dorin Emil Calbaza; Yvon Savaria (ISCAS (1), 1999)

Development of a high performance TSPC library for implementation of large digital building blocks. - B. Le Chapelain; A. Mechain; Yvon Savaria; Guy Bois (ISCAS (1), 1999)

A new approach to analyze interconnect delays in RC wire models. - Zhong-Fang Jin; Jean-Jacques Laurin; Yvon Savaria; Pierre Garon (ISCAS (6), 1999)

Spatial characterization of process variations via MOS transistor time constants in VLSI and WSI. - Mohamed Nekili; Yvon Savaria; Guy Bois (IEEE J. Solid State Circuits, 1999)

Generalization, discrimination, and multiple categorization using adaptive resonance theory. - Pierre Lavoie; Jean-François Crespo; Yvon Savaria (IEEE Trans. Neural Networks, 1999)

Reconfigurable pipelined 2-D convolvers for fast digital signal processing. - B. Bosi; Guy Bois; Yvon Savaria (IEEE Trans. Very Large Scale Integr. Syst., 1999)

A method to derive application-specific embedded processing cores. - Olivier Hébert; Ivan C. Kraljic; Yvon Savaria (CODES, 2000)

An efficient verification method for a class of multi-phase sequential circuits. - François-Raymond Boyer; El Mostapha Aboulhamid; Yvon Savaria (ICECS, 2000)

Very short locking time PLL based on controlled gain technique. - Youcef Fouzar; Mohamad Sawan; Yvon Savaria (ICECS, 2000)

Analysis of quantization effects in a digital hardware implementation of a fuzzy ART neural network algorithm. - Marc-André Cantin; Yves Blaquière; Yvon Savaria; Pierre Lavoie; Eric Granger (ISCAS, 2000)

A new fully integrated CMOS phase-locked loop with low jitter and fast lock time. - Youcef Fouzar; Mohamad Sawan; Yvon Savaria (ISCAS, 2000)

A methodology for validating digital circuits with mutation testing. - Patrice Vado; Yvon Savaria; Yannick Zoccarato; Chantal Robach (ISCAS, 2000)

Determining Schedules for Reducing Power Consumption Using Multiple Supply Voltages. - Noureddine Chabini; El Mostapha Aboulhamid; Yvon Savaria (ICCD, 2001)

An automatic word length determination method. - Marc-André Cantin; Yvon Savaria; D. Prodanos; Pierre Lavoie (ISCAS (5), 2001)

A new controlled gain phase-locked loop technique. - Youcef Fouzar; Yvon Savaria; Mohamad Sawan (ISCAS (4), 2001)

Minimizing process-induced skew using delay tuning. - Mohamed Nekili; Yvon Savaria; Guy Bois (ISCAS (4), 2001)

Performance estimators for hardware/software co-design. - Lévis Thériault; Daniel Audet; Yvon Savaria (ISCAS (5), 2001)

Methods for optimizing register placement in synchronous circuits derived using software pipelining techniques. - Noureddine Chabini; Yvon Savaria (ISSS, 2001)

Tools for the Characterization of Bipolar CML Testability. - Ginette Monté; Bernard Antaki; Serge Patenaude; Yvon Savaria; Claude Thibeault; Pieter M. Trouborst (VTS, 2001)

Direct digital frequency synthesis of low-jitter clocks. - Dorin Emil Calbaza; Yvon Savaria (IEEE J. Solid State Circuits, 2001)

Optimal design of synchronous circuits using software pipelining techniques. - François R. Boyer; El Mostapha Aboulhamid; Yvon Savaria; Michel Boyer (ACM Trans. Design Autom. Electr. Syst., 2001)

Yield Modeling of a WSI Telecom Router Architecture. - Bing Qiu 003; Yvon Savaria; Meng Lu; Chunyan Wang 004; Claude Thibeault (DFT, 2002)

A flexible floating-point format for optimizing data-paths and operators in FPGA based DSPs. - J. Dido; N. Géraudie; L. Loiseau; O. Payeur; Yvon Savaria; D. Poirier (FPGA, 2002)

Low-voltage bandgap reference with temperature compensation based on a threshold voltage technique. - A. Bendali; Yvon Savaria (ISCAS (3), 2002)

A CMOS phase-locked loop with an auto-calibrated VCO. - Youcef Fouzar; Yvon Savaria; Mohamad Sawan (ISCAS (3), 2002)

Architecture and performance characterization of hardware and software implementations of the Crozier frequency estimation algorithm. - L.-P. Lafrance; Marc-André Cantin; Yvon Savaria; S. H. Sung; Pierre Lavoie (ISCAS (4), 2002)

A linear phase detector for arbitrary clock signals. - Mathieu Renaud; Yvon Savaria (ISCAS (4), 2002)

FPGA Implementation of a Sub-pixel Correction Algorithm for Active Laser Range Finders. - Hakim Khali; Yvon Savaria (MVA, 2002)

A direct digital period synthesis circuit. - Dorin Emil Calbaza; Yvon Savaria (IEEE J. Solid State Circuits, 2002)

A practical approach to model long MIS interconnects in VLSI circuits. - Zhong-Fang Jin; Jean-Jacques Laurin; Yvon Savaria (IEEE Trans. Very Large Scale Integr. Syst., 2002)

IEEE 1149.1 Based Defect and Fault Tolerant Scan Chain for Wafer Scale Integration. - Meng Lu; Yvon Savaria; Bing Qiu 003; Jacques Taillefer (DFT, 2003)

Efficiency of Transient Bit-Flips Detection by Software Means: A Complete Study. - Bogdan Nicolescu; Paul Peronnard; Raoul Velazco; Yvon Savaria (DFT, 2003)

SIED: Software Implemented Error Detection. - Bogdan Nicolescu; Yvon Savaria; Raoul Velazco (DFT, 2003)

Unification of basic retiming and supply voltage scaling to minimize dynamic power consumption for synchronous digital designs. - Noureddine Chabini; Ismaïl Chabini; El Mostapha Aboulhamid; Yvon Savaria (ACM Great Lakes Symposium on VLSI, 2003)

A hardware-software co-design model for real-time 3D image computation using active laser range finders: a case study. - Hakim Khali; Yvon Savaria (ICECS, 2003)

A CMOS three-state frequency detector complementary to an enhanced linear phase detector for PLL, DLL or high frequency clock skew measurement. - Mathieu Renaud; Yvon Savaria (ISCAS (3), 2003)

A new memory reference reduction method for FFT implementation on DSP. - Yiyan Tang; Lie Qian; Yuke Wang; Yvon Savaria (ISCAS (4), 2003)

SoC platform architecture for a network processor. - Hany Ghattas; M. Mbaye; J. Pepga Bissou; Yvon Savaria (SoC, 2003)

Automating Functional Coverage Analysis Based on an Executable Specification. - S. Regimbal; Jean-Francois Lemire; Yvon Savaria; Guy Bois; El Mostapha Aboulhamid; A. Baron (IWSOC, 2003)

A Pattern Reordering Approach Based on Ambiguity Detection for Online Category Learning. - Eric Granger; Yvon Savaria; Pierre Lavoie (IEEE Trans. Pattern Anal. Mach. Intell., 2003)

Methods for minimizing dynamic power consumption in synchronous designs with multiple supply voltages. - Noureddine Chabini; Ismaïl Chabini; El Mostapha Aboulhamid; Yvon Savaria (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2003)

Improvement of sensor accuracy in the case of a variable surface reflectance gradient for active laser range finders. - Hakim Khali; Yvon Savaria; Jean-Louis Houle; Marc Rioux; J.-Angelo Beraldin; D. Poussart (IEEE Trans. Instrum. Meas., 2003)

An Integrated Test Platform for Nanostructure Electrical Characterization. - Olivier Duval; L.-P. Lafrance; Yvon Savaria; Patrick Desjardins (ICMENS, 2004)

The Effect of p-Coupling on the Electronic Properties of 1, 4-Dithiol Benzene Stacking. - Mohammed Layachi; Yvon Savaria; Alain Rochefort (ICMENS, 2004)

Performance Evaluation and Failure Rate Prediction for the Soft Implemented Error Detection Technique. - Bogdan Nicolescu; Yvon Savaria; Raoul Velazco (IOLTS, 2004)

Shunt-peaking in MCML gates and its application in the design of a 20 Gb/s half-rate phase detector. - Hung Tien Bui; Yvon Savaria (ISCAS (4), 2004)

An ADPLL circuit using a DDPS for genlock applications. - Dorin Emil Calbaza; Ioan Cordos; Nigel Seth-Smith; Yvon Savaria (ISCAS (4), 2004)

An on-chip delay measurements module for nanostructures characterization. - Olivier Duval; Yvon Savaria (ISCAS (3), 2004)

Spurs modeling in direct digital period synthesizers related to phase accumulator truncation. - Badre Izouggaghen; Abdelhakim Khouas; Yvon Savaria (ISCAS (3), 2004)

Assertion-based on-line verification and debug environment for complex hardware systems. - Kevin Peterson; Yvon Savaria (ISCAS (2), 2004)

10 GHz PLL Using Active Shunt-Peaked MCML Gates and Improved Frequency Acquisition XOR Phase Detector in 0.18 µm CMOS. - Hung Tien Bui; Yvon Savaria (IWSOC, 2004)

Interface-based Design of Systems-on-Chip using UML-RT. - Alexandre Chureau; Yvon Savaria; El Mostapha Aboulhamid (IWSOC, 2004)

A Framework for Implementing Reusable Digital Signal Processing Modules. - L.-P. Lafrance; Yvon Savaria (IWSOC, 2004)

An Intellectual Property Module for Auto-Calibration of Time-Interleaved Pipelined Analog-to-Digital Converters. - D. Morin; Frédéric Normandin; Marie-Eve Grandmaison; H. Dang; Yvon Savaria; Mohamad Sawan (IWSOC, 2004)

A Customizable Embedded SoC Platform Architecture. - Pascal Nsame; Yvon Savaria (IWSOC, 2004)

Verification Strategy Determination Using Dependence Analysis of Transaction-Level Models. - S. Regimbal; Yvon Savaria; Guy Bois (IWSOC, 2004)

Multi-processor SoC integration: a case study on BlueGene/L. - Pascal Nsame; Yvon Savaria (SoCC, 2004)

A Unified Environment to Assess Image Quality in Video Processing. - Marc-André Cantin; S. Regimbal; S. Catudal; Yvon Savaria (J. Circuits Syst. Comput., 2004)

The Role of Model-Level Transactors and UML in Functional Prototyping of Systems-on-Chip: A Software-Radio Application. - Alexandre Chureau; Yvon Savaria; El Mostapha Aboulhamid (DATE, 2005)

Gate oxide protection in HV CMOS/DMOS integrated circuits: Design and experimental results. - Robert Chebli; Mohamad Sawan; Yvon Savaria (ICECS, 2005)

Modeling power budget requirements of implantable electronic devices. - Saeid Hashemi; Mohamad Sawan; Yvon Savaria (ICECS, 2005)

Parameters estimation applied to automatic video processing algorithms validation. - S. Catudal; Marc-André Cantin; Yvon Savaria (ISCAS (4), 2005)

A novel approach for implementing ultra-high speed flash ADC using MCML circuits. - Dinh Hung Dang; Yvon Savaria; Mohamad Sawan (ISCAS (6), 2005)

Implementation of a cycle by cycle variable speed processor. - H. G. Epassa; François R. Boyer; Yvon Savaria (ISCAS (4), 2005)

A novel 2 GHz multi-layer AMBA high-speed bus interconnect matrix for SoC platforms. - Alexandre Landry; Mohamed Nekili; Yvon Savaria (ISCAS (4), 2005)

. A new switch compensation technique for inverted R-2R ladder DACs. - David Marche; Yves Gagnon; Yvon Savaria (ISCAS (1), 2005)

Application specific instruction-set processor generation for video processing based on loop optimization. - Maria Mbaye; Normand Bélanger; Yvon Savaria; Samuel Pierre (ISCAS (4), 2005)

Fast parameters optimization of an iterative decoder using a configurable hardware accelerator. - G. Provost; Marc-André Cantin; Mohamad Sawan; Christian Cardinal; Yvon Savaria; David Haccoun (ISCAS (4), 2005)

Design methods for CMOS low-current finely tunable voltage references covering a wide output range. - Simon Rioux; Alain Lacourse; Yvon Savaria; Michel Meunier (ISCAS (5), 2005)

A complete spurs distribution model for direct digital period synthesizers. - Max-Elie Salomon; Abdelhakim Khouas; Yvon Savaria (ISCAS (5), 2005)

Characterization of laser-induced photoexcitation effect on a surrounding CMOS ring oscillator. - Guillaume Wild; Yvon Savaria; Michel Meunier (ISCAS (4), 2005)

Analysis of Wave-Pipelined Domino Logic Circuit and Clocking Styles Subject to Parametric Variations. - Wei Ling; Yvon Savaria (ISQED, 2005)

A Generic Method for Embedded Measurement and Compensation of Process and Temperature Variations in SoCs. - Hung Tien Bui; Yvon Savaria (IWSOC, 2005)

Component-Based Methodology for Hardware Design of a Dataflow Processing Network. - Robert Grou-Szabo; Hany Ghattas; Yvon Savaria; Gabriela Nicolescu (IWSOC, 2005)

Performance Improvement of Configurable Processor Architectures Using a Variable Clock Period. - Bill Pontikakis; François R. Boyer; Yvon Savaria (IWSOC, 2005)

A HyperTransport Chip-to-Chip Interconnect Tunnel Developed Using SystemC. - Ami Castonguay; Yvon Savaria (IEEE International Workshop on Rapid System Prototyping, 2005)

A system level implementation strategy and partitioning heuristic for LUT-based applications. - Hakim Khali; Yvon Savaria; Jean-Louis Houle (Comput. Electr. Eng., 2005)

Scheduling and optimal register placement for synchronous circuits derived using software pipelining techniques. - Noureddine Chabini; El Mostapha Aboulhamid; Ismaïl Chabini; Yvon Savaria (ACM Trans. Design Autom. Electr. Syst., 2005)

Design of an Active-RC Bandpass Filter for a Subsampling RF Delta Modulator. - Ali Naderi; Mohamad Sawan; Yvon Savaria (CCECE, 2006)

Soft-error classification and impact analysis on real-time operating systems. - N. Ignat; Bogdan Nicolescu; Yvon Savaria; Gabriela Nicolescu (DATE, 2006)

Evaluation of a Software-Based Error Detection Technique by RT-Level Fault Injection. - Abdelaziz Ammari; Régis Leveugle; Bogdan Nicolescu; Yvon Savaria (DELTA, 2006)

High speed differential pulse-width control loop based on frequency-to-voltage converters. - Hung Tien Bui; Yvon Savaria (ACM Great Lakes Symposium on VLSI, 2006)

A Threshold-Based Deinterlacing Algorithm Using Motion Compensation and Directional Interpolation. - Hossein Mahvash Mohammadi; J. M. Pierre Langlois; Yvon Savaria (ICECS, 2006)

Architecture of a hypertransport tunnel. - Ami Castonguay; Yvon Savaria (ISCAS, 2006)

A power planning model for implantable stimulators. - Saeid Hashemi; Mohamad Sawan; Yvon Savaria (ISCAS, 2006)

High-voltage operational amplifier based on dual floating-gate transistors. - Z. Huang; Yvon Savaria; Mohamad Sawan; R. Meinga (ISCAS, 2006)

Design exploration with an application-specific instruction-set processor for ELA deinterlacing. - Maria Mbaye; D. Lebel; Normand Bélanger; Yvon Savaria; Samuel Pierre (ISCAS, 2006)

A novel 2-GHz band-pass delta modulator dedicated to wireless receivers. - Ali Naderi; Mohamad Sawan; Yvon Savaria (ISCAS, 2006)

A 0.8V algorithmically defined buffer and ring oscillator low-energy design for nanometer SoCs. - Bill Pontikakis; François R. Boyer; Yvon Savaria (ISCAS, 2006)

Zero skew differential clock distribution network. - Houman Zarrabi; Haydar Saaied; Asim J. Al-Khalili; Yvon Savaria (ISCAS, 2006)

Validation by Fault Injection of a Software Error Detection Technique Dealing with Critical Single Event Upsets. - S. Torrellas; Bogdan Nicolescu; Raul Velazco; Mario García-Valderas; Yvon Savaria (LATW, 2006)

Motion Compensated Frame Rate Conversion Using a Specialized Instruction Set Processor. - Nicolas Beucher; Normand Bélanger; Yvon Savaria; Guy Bois (SiPS, 2006)

A Metric for Automatic Word-Length Determination of Hardware Datapaths. - Marc-André Cantin; Yvon Savaria; D. Prodanos; Pierre Lavoie (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006)

New Analog Test Metrics Based on Probabilistic and Deterministic Combination Approaches. - Abdessatar Abderrahman; Mohamad Sawan; Yvon Savaria; Abdelhakim Khouas (ICECS, 2007)

A Methodology to Evaluate the Energy Efficiency of Application Specific Processors. - Nicolas Beucher; Normand Bélanger; Yvon Savaria; Guy Bois (ICECS, 2007)

Digital Measurement Technique for Capacitance Variation Detection on Integrated Circuit I/Os. - Yves Blaquière; Yvon Savaria; Jaouad El Fouladi (ICECS, 2007)

An FPGA Implementation of a Scalable Network-on-Chip Based on the Token Ring Concept. - Karim Hadjiat; Francis St-Pierre; Guy Bois; Yvon Savaria; Michel Langevin; Pierre G. Paulin (ICECS, 2007)

Iterative Noise-Compensated Method to Improve LPC Based Speech Analysis. - Abdelaziz Trabelsi; François-Raymond Boyer; Yvon Savaria; Mounir Boukadoum (ICECS, 2007)

Signal Integrity Analysis of a High Precision D/A Converter. - Olivier Valorge; David Marche; Alain Lacourse; Mohamad Sawan; Yvon Savaria (ICECS, 2007)

Modeling the Substrate Noise Injected by a DC-DC Converter. - Vincent Binet; Yvon Savaria; Michel Meunier; Yves Gagnon (ISCAS, 2007)

High-Voltage DMOS Integrated Circuits with Floating Gate Protection Technique. - Robert Chebli; Mohamad Sawan; Yvon Savaria; Kamal El-Sankary (ISCAS, 2007)

Crosstalk Effects in Event-Driven Self-Timed Circuits Designed With 90nm CMOS Technology. - Syed Rafay Hasan; Yvon Savaria (ISCAS, 2007)

A Low-Complexity High-Speed Clock Generator for Dynamic Frequency Scaling of FPGA and Standard-Cell Based Designs. - Bill Pontikakis; Hung Tien Bui; François R. Boyer; Yvon Savaria (ISCAS, 2007)

Integrated Circuit Trimming Technique for Offset Reduction in a Precision CMOS Amplifier. - Rahul Singh; Yves Audet; Yves Gagnon; Yvon Savaria (ISCAS, 2007)

Constraint-based model for network service provisioning. - Rudy Deca; Omar Cherkaoui; Yvon Savaria; Doug Slone (Ann. des Télécommunications, 2007)

A high-level requirements engineering methodology for electronic system-level design. - Nicolas Gorse; P. Bélanger; Alexandre Chureau; El Mostapha Aboulhamid; Yvon Savaria (Comput. Electr. Eng., 2007)

A Five-Field Motion Compensated Deinterlacing Method Based on Vertical Motion. - Hossein Mahvash Mohammadi; J. M. Pierre Langlois; Yvon Savaria (IEEE Trans. Consumer Electron., 2007)

A Novel Application-specific Instruction-set Processor Design Approach for Video Processing Acceleration. - Mame Maria Mbaye; Normand Bélanger; Yvon Savaria; Samuel Pierre (J. VLSI Signal Process., 2007)

A very-high output impedance current mirror for very-low voltage biomedical analog circuits. - Louis-François Tanguay; Mohamad Sawan; Yvon Savaria (APCCAS, 2008)

Loop-oriented metrics for exploring an application-specific architecture design-space. - Maria Mbaye; Normand Bélanger; Yvon Savaria; Samuel Pierre (ASAP, 2008)

Hardware/software system co-verification of an active reconfigurable board with SystemC-VHDL. - Yan Basile-Bellavance; Etienne Lepercq; Yves Blaquière; Yvon Savaria (ICECS, 2008)

Digital signal propagation on a wafer-scale smart active programmable interconnect. - Olivier Valorge; Anh Tuan Nguyen; Yves Blaquière; Richard Norman; Yvon Savaria (ICECS, 2008)

Modeling and simulation of complex heterogeneous systems. - Amine Anane; El Mostapha Aboulhamid; Julie Vachon; Yvon Savaria (ISCAS, 2008)

Design of a High-Speed Differential Frequency-to-Voltage Converter and Its Application in a 5-GHz Frequency-Locked Loop. - Hung Tien Bui; Yvon Savaria (IEEE Trans. Circuits Syst. I Regul. Pap., 2008)

Laser Fine-Tuneable Deep-Submicrometer CMOS 14-bit DAC. - David Marche; Yvon Savaria; Yves Gagnon (IEEE Trans. Circuits Syst. I Regul. Pap., 2008)

On the Design of Undersampling Continuous-Time Bandpass Delta-Sigma Modulators for Gigahertz Frequency A/D Conversion. - Ali Naderi; Mohamad Sawan; Yvon Savaria (IEEE Trans. Circuits Syst. I Regul. Pap., 2008)

Spur Model for a Fixed-Frequency Signal Subject to Periodic Jitter. - Max-Elie Salomon; Badre Izouggaghen; Abdelhakim Khouas; Yvon Savaria (IEEE Trans. Instrum. Meas., 2008)

Guest Editorial: 20 Years of ASAP. - Wayne Luk; Yvon Savaria; Oskar Mencer (J. Signal Process. Syst., 2008)

An interconnect-aware delay model for dynamic voltage scaling in NM technologies. - Houman Zarrabi; Asim J. Al-Khalili; Yvon Savaria (ACM Great Lakes Symposium on VLSI, 2009)

A low-area power-efficient CMOS active rectifier for wirelessly powered medical devices. - Saeid Hashemi; Mohamad Sawan; Yvon Savaria (ICECS, 2009)

Estimation of energy performance in computing platforms. - Houman Zarrabi; Asim J. Al-Khalili; Yvon Savaria (ICECS, 2009)

An All-digital Skew-adaptive Clock Scheduling Algorithm for Heterogeneous Multiprocessor Systems on Chips (MPSoCs). - Syed Rafay Hasan; Bill Pontikakis; Yvon Savaria (ISCAS, 2009)

Workflow for an Electronic Configurable Prototyping System. - Etienne Lepercq; Yves Blaquière; Richard Norman; Yvon Savaria (ISCAS, 2009)

A low-power 2GHz data conversion using delta modulation for portable application. - Ali Naderi; Mohamad Sawan; Yvon Savaria (Integr., 2009)

A novel low-drop CMOS active rectifier for RF-powered devices: Experimental results. - Saeid Hashemi; Mohamad Sawan; Yvon Savaria (Microelectron. J., 2009)

A very-high output impedance charge pump for low-voltage low-power PLLs. - Louis-François Tanguay; Mohamad Sawan; Yvon Savaria (Microelectron. J., 2009)

An Improved Switch Compensation Technique for Inverted R-2R Ladder DACs. - David Marche; Yvon Savaria; Yves Gagnon (IEEE Trans. Circuits Syst. I Regul. Pap., 2009)

Performance Characterization for the Implementation of Content Addressable Memories Based on Parallel Hashing Memories. - Patrick Mahoney; Yvon Savaria; Guy Bois; Patrice Plante (Trans. High Perform. Embed. Archit. Compil., 2009)

High Acceleration for Video Processing Applications Using Specialized Instruction Set Based on Parallelism and Data Reuse. - Nicolas Beucher; Normand Bélanger; Yvon Savaria; Guy Bois (J. Signal Process. Syst., 2009)

Thermo-mechanical analysis of a reconfigurable wafer-scale integrated circuit. - Mohammed Bougataya; Oussama Berriah; Ahmed Lakhssassi; Adel-Omar Dahmane; Yves Blaquière; Yvon Savaria; Richard Norman; Richard Prytula (ICECS, 2010)

A spatially reconfigurable fast differential interface for a wafer scale configurable platform. - Olivier Valorge; Yves Blaquière; Yvon Savaria (ICECS, 2010)

Fully integrated ultra-low-power asynchronously driven step-down DC-DC converter. - Omar Al-Terkawi Hasib; Mohamad Sawan; Yvon Savaria (ISCAS, 2010)

An interconnect-aware Dynamic Voltage Scaling scheme for DSM VLSI. - Houman Zarrabi; Asim J. Al-Khalili; Yvon Savaria (ISCAS, 2010)

Crosstalk Glitch Propagation Modeling for Asynchronous Interfaces in Globally Asynchronous Locally Synchronous Systems. - Syed Rafay Hasan; Normand Bélanger; Yvon Savaria; M. Omair Ahmad (IEEE Trans. Circuits Syst. I Regul. Pap., 2010)

Crosstalk-Glitch Gating: A Solution for Designing Glitch-Tolerant Asynchronous Handshake Interface Mechanisms for GALS Systems. - Syed Rafay Hasan; Normand Bélanger; Yvon Savaria; M. Omair Ahmad (IEEE Trans. Circuits Syst. I Regul. Pap., 2010)

Modeling R-2R Segmented-Ladder DACs. - David Marche; Yvon Savaria (IEEE Trans. Circuits Syst. I Regul. Pap., 2010)

Repeater insertion in power-managed VLSI systems. - Houman Zarrabi; Asim J. Al-Khalili; Yvon Savaria (ACM Great Lakes Symposium on VLSI, 2011)

A tracking algorithm suitable for embedded systems implementation. - Rana Farah; Qifeng Gan; J. M. Pierre Langlois; Guillaume-Alexandre Bilodeau; Yvon Savaria (ICECS, 2011)

SEGP-Finder: Tool for identification of Soft Error Glitch-Propagating paths at gate level. - Ghaith Bany Hamad; Otmane Aït Mohamed; Syed Rafay Hasan; Yvon Savaria (ICECS, 2011)

A GPGPU-based software implementation of the PBDI deinterlacing algorithm. - Gilbert Kowarzyk; Normand Bélanger; Yvon Savaria (ICECS, 2011)

Customized embedded processor design for global photographic tone mapping. - Shervin Vakili; Diana Carolina Gil; J. M. Pierre Langlois; Yvon Savaria; Guy Bois (ICECS, 2011)

Activity management in battery-powered embedded systems: A case study of ZigBee® WSN. - Houman Zarrabi; A. J. Al-Khalili; Yvon Savaria (ICECS, 2011)

Comparative analysis of contrast enhancement algorithms in surveillance imaging. - Diana Carolina Gil; Rana Farah; J. M. Pierre Langlois; Guillaume-Alexandre Bilodeau; Yvon Savaria (ISCAS, 2011)

Analysis of Resistive Open Defects in Drowsy SRAM Cells. - Afshin Nourivand; Asim J. Al-Khalili; Yvon Savaria (J. Electron. Test., 2011)

All digital skew tolerant synchronous interfacing methods for high-performance point-to-point communications in deep sub-micron SoCs. - Syed Rafay Hasan; Normand Bélanger; Yvon Savaria; M. Omair Ahmad (Integr., 2011)

A Low-Power Asynchronous Step-Down DC-DC Converter for Implantable Devices. - Omar Al-Terkawi Hasib; Mohamad Sawan; Yvon Savaria (IEEE Trans. Biomed. Circuits Syst., 2011)

A Laser-Trimmed Rail-to-Rail Precision CMOS Operational Amplifier. - Rahul Singh; Yves Audet; Yves Gagnon; Yvon Savaria; Étienne Boulais; Michel Meunier (IEEE Trans. Circuits Syst. II Express Briefs, 2011)

Optimal scheduling policy for AFDX End-Systems with virtual links of identical bandwidth allocation gap size. - Romain Nishi; Guchuan Zhu; Yvon Savaria (CCECE, 2012)

A novel hybrid FIFO asynchronous clock domain crossing interfacing method. - Zaid Al-bayati; Otmane Aït Mohamed; Syed Rafay Hasan; Yvon Savaria (ACM Great Lakes Symposium on VLSI, 2012)

Two-level configuration for FPGA: A new design methodology based on a computing fabric. - Mathieu Allard; Patrick Grogan; Yvon Savaria; Jean-Pierre David (ISCAS, 2012)

Identification of soft error glitch-propagation paths: Leveraging SAT solvers. - Ghaith Bany Hamad; Otmane Aït Mohamed; Syed Rafay Hasan; Yvon Savaria (ISCAS, 2012)

Propagating analog signals through a fully digital network on an electronic system prototyping platform. - Omar Al-Terkawi Hasib; Walder Andre; Yves Blaquière; Yvon Savaria (ISCAS, 2012)

State-holding free NULL Convention Logic™. - Jean-François Pons; Jean-Jules Brault; Yvon Savaria (MWSCAS, 2012)

Probabilistic model checking of clock domain crossing interfaces. - Zaid Al-bayati; Otmane Aït Mohamed; Yvon Savaria; Mounir Boukadoum (NEWCAS, 2012)

An FPGA compatible asynchronous wake-up receiver for Wireless Sensor Networks. - Jean-François Pons; Jean-Jules Brault; Yvon Savaria (NEWCAS, 2012)

A new approach for pin detection for an electronic system prototyping reconfigurable platform. - Hai H. Nguyen; Mikael Guillemot; Yvon Savaria; Yves Blaquière (RSP, 2012)

System modeling and multicore simulation using transactions. - Amine Anane; El Mostapha Aboulhamid; Yvon Savaria (ICSAMOS, 2012)

Rule-Based Network Service Provisioning. - Rudy Deca; Omar Cherkaoui; Yvon Savaria (J. Networks, 2012)

A High-Efficiency Low-Voltage CMOS Rectifier for Harvesting Energy in Implantable Devices. - Saeid Hashemi; Mohamad Sawan; Yvon Savaria (IEEE Trans. Biomed. Circuits Syst., 2012)

Efficient Search Algorithm for Determining Optimal R=1/2 Systematic Convolutional Self-Doubly Orthogonal Codes. - Gilbert Kowarzyk; N. Blanger; David Haccoun; Yvon Savaria (IEEE Trans. Commun., 2012)

Real-Time Computation of Local Neighborhood Functions in Application-Specific Instruction-Set Processors. - P. Aubertin; J. M. Pierre Langlois; Yvon Savaria (IEEE Trans. Very Large Scale Integr. Syst., 2012)

Loop Acceleration Exploration for ASIP Architecture. - Mame Maria Mbaye; Normand Bélanger; Yvon Savaria; Samuel Pierre (IEEE Trans. Very Large Scale Integr. Syst., 2012)

Postsilicon Tuning of Standby Supply Voltage in SRAMs to Reduce Yield Losses Due to Parametric Data-Retention Failures. - Afshin Nourivand; Asim J. Al-Khalili; Yvon Savaria (IEEE Trans. Very Large Scale Integr. Syst., 2012)

Software rendering methods to display wafer scale integrated circuit dataset. - Mikael Guillemot; Yves Blaquière; Yvon Savaria (CCECE, 2013)

Accelerating a modified Gaussian pyramid with a customized processor. - Diana Carolina Gil; J. M. Pierre Langlois; Yvon Savaria (DASIP, 2013)

Early Analysis of Soft Error Effects for Aerospace Applications Using Probabilistic Model Checking. - Khaza Anuarul Hoque; Otmane Aït Mohamed; Yvon Savaria; Claude Thibeault (FTSCS, 2013)

Optimal packet classification applicable tothe OpenFlow context. - Thibaut Stimpfling; Yvon Savaria; André Béliveau; Normand Bélanger; Omar Cherkaoui (HPPN@HPDC, 2013)

A spatiotemporal attention operator for monitoring thermo-mechanical stress in wafer-scale integrated circuits using an infrared camera. - Ahmed Lakhssassi; Roman Palenychka; Michel Sayde; Yvon Savaria; Marek B. Zaremba; Emmanuel Kengne (ISPA, 2013)

An interface for the I2C protocol in the WaferBoard™. - Wasim Hussain; Yvon Savaria; Yves Blaquière (ISCAS, 2013)

A reformulated systematic resampling algorithm for particle filters and its parallel implementation in an application-specific instruction-set processor. - Qifeng Gan; J. M. Pierre Langlois; Yvon Savaria (MWSCAS, 2013)

A netlist pruning tool for an electronic system prototyping platform. - Karim Baratli; Ahmed Lakhssassi; Yves Blaquière; Yvon Savaria (NEWCAS, 2013)

A methodology for system-level fault injection based on gate-level faulty behavior. - R. Robache; Jean-François Boland; Claude Thibeault; Yvon Savaria (NEWCAS, 2013)

A 2D Gaussian smoothing kernel mapped to heterogeneous platforms. - Abdelaziz Trabelsi; Yvon Savaria (NEWCAS, 2013)

A Library-Based Early Soft Error Sensitivity Analysis Technique for SRAM-Based FPGA Design. - Claude Thibeault; Yassine Hariri; Syed Rafay Hasan; Christelle Hobeika; Yvon Savaria; Yves Audet; Fatima Zahra Tazi (J. Electron. Test., 2013)

Efficient Parallel Search Algorithm for Determining Optimal R=1/2 Systematic Convolutional Self-Doubly Orthogonal Codes. - Gilbert Kowarzyk; Normand Bélanger; David Haccoun; Yvon Savaria (IEEE Trans. Commun., 2013)

Constraint-based configuration complexity model for autonomic network configuration management. - Rudy Deca; Omar Cherkaoui; Yvon Savaria (GIIS, 2014)

Probabilistic model checking of single event transient propagation at RTL level. - Ghaith Bany Hamad; Otmane Aït Mohamed; Yvon Savaria (ICECS, 2014)

A data-driven energy efficient and flexible compute fabric architecture: For adaptive computing applied to ULSI of FFT. - Pascal Nsame; Guy Bois; Yvon Savaria (ICECS, 2014)

Neuromuscular Representation and Synthetic Generation of Handwritten Whiteboard Notes. - Andreas Fischer 002; Réjean Plamondon; Christian O'Reilly; Yvon Savaria (ICFHR, 2014)

Design and validation of a novel reconfigurable and defect tolerant JTAG scan chain. - Yves Blaquière; Yan Basile-Bellavance; Safa Berrima; Yvon Savaria (ISCAS, 2014)

Abstracting Single Event Transient characteristics variations due to input patterns and fan-out. - Ghaith Bany Hamad; Syed Rafay Hasan; Otmane Aït Mohamed; Yvon Savaria (ISCAS, 2014)

Vt-conscious repeater insertion in power-managed VLSI. - Houman Zarrabi; Asim J. Al-Khalili; Yvon Savaria (ISIC, 2014)

Probabilistic model checking based DAL analysis to optimize a combined TMR-blind-scrubbing mitigation technique for FPGA-based aerospace applications. - Khaza Anuarul Hoque; Otmane Aït Mohamed; Yvon Savaria; Claude Thibeault (MEMOCODE, 2014)

Modeling, analyzing, and abstracting single event transient propagation at gate level. - Ghaith Bany Hamad; Syed Rafay Hasan; Otmane Aït Mohamed; Yvon Savaria (MWSCAS, 2014)

Adaptive real-time DSP acceleration for SoC applications. - Pascal Nsame; Guy Bois; Yvon Savaria (MWSCAS, 2014)

Design and Test of Adaptive Computing Fabrics for Scalable and High-Efficiency Cognitive SoC Applications. - Pascal Nsame; Guy Bois; Yvon Savaria (NATW, 2014)

A memory transaction model for Sparse Matrix-Vector multiplications on GPUs. - Thalie Keklikian; J. M. Pierre Langlois; Yvon Savaria (NEWCAS, 2014)

A current-output DAC for low-power low-noise log-domain ΔΣ modulators. - Mohamed A. Shaheen; Anas A. Hamoui; Yvon Savaria (NEWCAS, 2014)

A Hausdorff Heuristic for Efficient Computation of Graph Edit Distance. - Andreas Fischer 002; Réjean Plamondon; Yvon Savaria; Kaspar Riesen; Horst Bunke (S+SSPR, 2014)

On Delay Faults Affecting I/O Blocks of an SRAM-Based FPGA Due to Ionizing Radiations. - Fatima Zahra Tazi; Claude Thibeault; Yvon Savaria; Simon Pichette; Yves Audet (CoRR, 2014)

A Parallel Systematic Resampling Algorithm for High-Speed Particle Filters in Embedded Systems. - Qifeng Gan; J. M. Pierre Langlois; Yvon Savaria (Circuits Syst. Signal Process., 2014)

A computationally efficient importance sampling tracking algorithm. - Rana Farah; Qifeng Gan; J. M. Pierre Langlois; Guillaume-Alexandre Bilodeau; Yvon Savaria (Mach. Vis. Appl., 2014)

A Configurable Multi-Rail Power and I/O Pad Applied to Wafer-Scale Systems. - Nicolas Laflamme-Mayer; Yves Blaquière; Yvon Savaria; Mohamad Sawan (IEEE Trans. Circuits Syst. I Regul. Pap., 2014)

Determinism Enhancement of AFDX Networks via Frame Insertion and Sub-Virtual Link Aggregation. - Meng Li 003; Michaël Lauer; Guchuan Zhu; Yvon Savaria (IEEE Trans. Ind. Informatics, 2014)

Optimizing the Parallel Tree-Search for Finding Shortest-Span Error-Correcting CDO Codes. - Gilbert Kowarzyk; Normand Bélanger; David Haccoun; Yvon Savaria (IEEE Trans. Parallel Distributed Syst., 2014)

Efficient Uniform Quantization Likelihood Evaluation for Particle Filters in Embedded Implementations. - Qifeng Gan; J. M. Pierre Langlois; Yvon Savaria (J. Signal Process. Syst., 2014)

Design Intelligence for Interconnection Realization in Power-Managed SoCs. - Houman Zarrabi; A. J. Al-Khalili; Yvon Savaria (Computational Intelligence in Digital and Network Designs and Applications, 2015)

Mapping applications on two-level configurable hardware. - Himan Khanzadi; Yvon Savaria; Jean-Pierre David (AHS, 2015)

Towards an accurate reliability, availability and maintainability analysis approach for satellite systems based on probabilistic model checking. - Khaza Anuarul Hoque; Otmane Aït Mohamed; Yvon Savaria (DATE, 2015)

Harvesting energy from data lines for avionics applications: Power conversion chain architecture. - Maryam Mohajertehrani; Umar Shafique; Yvon Savaria; Mohamad Sawan (ICM, 2015)

Efficient multilevel formal analysis and estimation of design vulnerability to Single Event Transients. - Ghaith Bany Hamad; Otmane Aït Mohamed; Yvon Savaria (IOLTS, 2015)

Defect diagnosis algorithms for a field programmable interconnect network embedded in a Very Large Area Integrated Circuit. - Gontran Sion; Yves Blaquière; Yvon Savaria (IOLTS, 2015)

Modeling the faulty behaviour of digital designs using a feed forward neural network approach. - Zeynab Mirzadeh; Jean-François Boland; Yvon Savaria (ISCAS, 2015)

Analysis and characterization of data energy tradeoffs: For VLSI architectural agility in C-RAN platforms. - Pascal Nsame; Guy Bois; Yvon Savaria (ISCAS, 2015)

Power-efficient hardware architecture for computing Split-Radix FFTs on highly sparsed spectrum. - Hanieh Abdollahifakhr; Normand Bélanger; Yvon Savaria; François Gagnon (NEWCAS, 2015)

DPDK and MKL; Enabling technologies for near deterministic cloud-based signal processing. - Roya Alizadeh; Normand Bélanger; Yvon Savaria; Jean-François Frigon (NEWCAS, 2015)

Self-timed circuits FPGA implementation flow. - Mickaël Fiorentino; Omar Al-Terkawi Hasib; Yvon Savaria; Claude Thibeault (NEWCAS, 2015)

Parallel independent FFT implementation on intel processors and Xeon phi for LTE and OFDM systems. - Mounir Khelifi; Daniel Massicotte; Yvon Savaria (NORCAS, 2015)

Characterizing, modeling, and analyzing soft error propagation in asynchronous and synchronous digital circuits. - Ghaith Bany Hamad; Syed Rafay Hasan; Otmane Aït Mohamed; Yvon Savaria (Microelectron. Reliab., 2015)

An Interface for Open-Drain Bidirectional Communication in Field Programmable Interconnection Networks. - Wasim Hussain; Yves Blaquière; Yvon Savaria (IEEE Trans. Circuits Syst. I Regul. Pap., 2015)

Efficient identification of Faces in video Streams using low-Power Multi-Core Devices. - Donavan Prieur; Eric Granger; Yvon Savaria; Claude Thibeault (Handbook of Pattern Recognition and Computer Vision, 2016)

Memory-Efficient String Matching for Intrusion Detection Systems using a High-Precision Pattern Grouping Algorithm. - Shervin Vakili; J. M. Pierre Langlois; Bochra Boughzala; Yvon Savaria (ANCS, 2016)

Detailed analysis of radiation-induced delays on I/O blocks of an SRAM-based FPGA. - Fatima Zahra Tazi; Claude Thibeault; Yvon Savaria (CCECE, 2016)

Efficient probabilistic fault tree analysis of safety critical systems via probabilistic model checking. - Marwan Ammar; Ghaith Bany Hamad; Otmane Aït Mohamed; Yvon Savaria (FDL, 2016)

Comprehensive non-functional analysis of combinational circuits vulnerability to single event transients. - Ghaith Bany Hamad; Ghaith Kazma; Otmane Aït Mohamed; Yvon Savaria (FDL, 2016)

Efficient and accurate analysis of single event transients propagation using SMT-based techniques. - Ghaith Bany Hamad; Ghaith Kazma; Otmane Aït Mohamed; Yvon Savaria (ICCAD, 2016)

Performance analysis of a reduced complexity SCMA decoder exploiting a low-complexity maximum-likelihood approximation. - Roya Alizadeh; Yvon Savaria (ICECS, 2016)

Investigating the efficiency and accuracy of a data type reduction technique for soft error analysis. - Ghaith Kazma; Ghaith Bany Hamad; Otmane Aït Mohamed; Yvon Savaria (ICECS, 2016)

A practical design method for prototyping self-timed processors using FPGAs. - Mickaël Fiorentino; Yvon Savaria; Claude Thibeault; Pascal Gervais (ISCAS, 2016)

Towards formal abstraction, modeling, and analysis of Single Event Transients at RTL. - Ghaith Bany Hamad; Otmane Aït Mohamed; Yvon Savaria (ISCAS, 2016)

Wireless power transfer through metallic barriers enclosing a harsh environment; feasibility and preliminary results. - Ahmad Hassan; Aref Trigui; Umar Shafique; Yvon Savaria; Mohamad Sawan (ISCAS, 2016)

A compact spatially configurable differential input stage for a field programmable interconnection network. - Wasim Hussain; Yvon Savaria; Yves Blaquière (ISCAS, 2016)

Towards efficient and concurrent FFTs implementation on Intel Xeon/MIC clusters for LTE and HPC. - Mounir Khelifi; Daniel Massicotte; Yvon Savaria (ISCAS, 2016)

Performance characterization of an SCMA decoder. - Roya Alizadeh; Normand Bélanger; Yvon Savaria; François R. Boyer (NEWCAS, 2016)

A fast systolic priority queue architecture for a flow-based Traffic Manager. - Imad Benacer; François-Raymond Boyer; Normand Bélanger; Yvon Savaria (NEWCAS, 2016)

Towards LTE physical layer virtualization on a COTS multicore platform with efficient scheduling. - Michel Gemieux; Yvon Savaria; Guchuan Zhu; Jean-François Frigon (NEWCAS, 2016)

Quad-Level Carrier Width Modulation demodulator for micro-implants. - Aref Trigui; Mohamed Ali 001; Ahmed Chiheb Ammari; Yvon Savaria; Mohamad Sawan (NEWCAS, 2016)

Applying formal verification to early assessment of FPGA-based aerospace applications: Methodology and experience. - Khaza Anuarul Hoque; Otmane Aït Mohamed; Yvon Savaria (SysCon, 2016)

WeSPer: A flexible small delay defect quality metric. - Omar Al-Terkawi Hasib; Yvon Savaria; Claude Thibeault (VTS, 2016)

A novel spatially configurable differential interface for an electronic system prototyping platform. - Wasim Hussain; Olivier Valorge; Yves Blaquière; Yvon Savaria (Integr., 2016)

An Asynchronous Delta-Modulator Based A/D Converter for an Electronic System Prototyping Platform. - Wasim Hussain; Hussein Fakhoury; Patricia Desgreys; Yves Blaquière; Yvon Savaria (IEEE Trans. Circuits Syst. I Regul. Pap., 2016)

Monitoring Thermal Stress in Wafer-Scale Integrated Circuits by the Attentive Vision Method Using an Infrared Camera. - Ahmed Lakhssassi; Roman Palenychka; Yvon Savaria; Michel Sayde; Marek B. Zaremba (IEEE Trans. Circuits Syst. Video Technol., 2016)

Joint power control and beamformer design with antenna selection. - Faika Hoque; Yvon Savaria; Christian Cardinal (CCECE, 2017)

An FPGA Overlay Architecture for Cost Effective Regular Expression Search (Abstract Only). - Thomas Luinaud; Yvon Savaria; J. M. Pierre Langlois (FPGA, 2017)

Analysis of SEU Propagation in Combinational Circuits at RTL Based on Satisfiability Modulo Theories. - Ghaith Kazma; Ghaith Bany Hamad; Otmane Aït Mohamed; Yvon Savaria (ACM Great Lakes Symposium on VLSI, 2017)

An FPGA Coarse Grained Intermediate Fabric for Regular Expression Search. - Thomas Luinaud; Yvon Savaria; J. M. Pierre Langlois (ACM Great Lakes Symposium on VLSI, 2017)

Comprehensive analysis of sequential circuits vulnerability to transient faults using SMT. - Ghaith Bany Hamad; Ghaith Kazma; Otmane Aït Mohamed; Yvon Savaria (IOLTS, 2017)

A multi-measurements RO-TDC implemented in a Xilinx field programmable gate array. - Safa Berrima; Yves Blaquière; Yvon Savaria (ISCAS, 2017)

Scalable memory-less architecture for string matching with FPGAs. - Ideh Sarbishei; Shervin Vakili; J. M. Pierre Langlois; Yvon Savaria (ISCAS, 2017)

A Cache-Coherent Heterogeneous Architecture for Low Latency Real Time Applications. - Michel Gemieux; Yvon Savaria; Jean-Pierre David; Guchuan Zhu (ISORC, 2017)

Sub-ps resolution programmable delays implemented in a Xilinx FPGA. - Safa Berrima; Yves Blaquière; Yvon Savaria (MWSCAS, 2017)

A high-speed traffic manager architecture for flow-based networking. - Imad Benacer; François-Raymond Boyer; Yvon Savaria (NEWCAS, 2017)

FPGA implementation of Token-based Self-timed processors: A case study. - Mickaël Fiorentino; Yvon Savaria; Claude Thibeault (NEWCAS, 2017)

Improving performance of SCMA MPA decoders using estimation of conditional probabilities. - Alireza Ghaffari; Mathieu Léonardon; Yvon Savaria; Christophe Jégo; Camille Leroux (NEWCAS, 2017)

Stability of GaN150-based HEMT in high temperature up to 400°C. - Ahmad Hassan; Mohamed Ali 001; Aref Trigui; Sami Hached; Yvon Savaria; Mohamad Sawan (NEWCAS, 2017)

Analysis of SEU propagation in sequential circuits at RTL using Satisfiability Modulo Theories. - Ghaith Kazma; Ghaith Bany Hamad; Otmane Aït Mohamed; Yvon Savaria (NEWCAS, 2017)

A data driven CGRA Overlay Architecture with embedded processors. - Himan Khanzadi; Yvon Savaria; Jean-Pierre David (NEWCAS, 2017)

A 14.5 µW generic Carrier Width demodulator for telemetry-based Medical Devices. - Aref Trigui; Mohamed Ali 001; Ahmed Chiheb Ammari; Yvon Savaria; Mohamad Sawan (NEWCAS, 2017)

A DAQM-Based Load Balancing Scheme for High Performance Computing Platforms. - Kaijun Yang; Meng Li 003; Guchuan Zhu; Yvon Savaria (IEEE Access, 2017)

Extensions to decision-tree based packet classification algorithms to address new classification paradigms. - Thibaut Stimpfling; Normand Bélanger; Omar Cherkaoui; André Béliveau; Ludovic Béliveau; Yvon Savaria (Comput. Networks, 2017)

Formal Methods Based Synthesis of Single Event Transient Tolerant Combinational Circuits. - Ghaith Bany Hamad; Otmane Aït Mohamed; Yvon Savaria (J. Electron. Test., 2017)

Formal analysis of SEU mitigation for early dependability and performability analysis of FPGA-based space applications. - Khaza Anuarul Hoque; Otmane Aït Mohamed; Yvon Savaria (J. Appl. Log., 2017)

Reliability Enhancement of Redundancy Management in AFDX Networks. - Meng Li 003; Guchuan Zhu; Yvon Savaria; Michaël Lauer (IEEE Trans. Ind. Informatics, 2017)

A Low-Latency Memory-Efficient IPv6 Lookup Engine Implemented on FPGA Using High-Level Synthesis. - Thibaut Stimpfling; J. M. Pierre Langlois; Normand Bélanger; Yvon Savaria (CCGrid, 2018)

Reliability Analysis of the SPARC V8 Architecture via Fault Trees and UPPAL-SMC. - Marwan Ammar; Ghaith Bany Hamad; Otmane Aït Mohamed; Yvon Savaria (ICECS, 2018)

Vector Matrix Multiplication Using Crossbar Arrays: A Comparative Analysis. - Hussein Assaf; Yvon Savaria; Mohamad Sawan (ICECS, 2018)

High-Temperature Modeling of the I-V Characteristics of GaN150 HEMT Using Machine Learning Techniques. - Ahmed Abubakr; Ahmad Hassan; Ahmed Ragab; Soumaya Yacout; Yvon Savaria; Mohamad Sawan (ISCAS, 2018)

High-Temperature Empirical Modeling for the I-V Characteristics of GaN150-Based HEMT. - Mostafa Amer; Ahmad Hassan; Ahmed Ragab; Soumaya Yacout; Yvon Savaria; Mohamad Sawan (ISCAS, 2018)

Design of a Low Latency 40 Gb/s Flow-Based Traffic Manager Using High-Level Synthesis. - Imad Benacer; François-Raymond Boyer; Yvon Savaria (ISCAS, 2018)

Implementation of a Cache-Based IPv6 Lookup System with Hashing. - Bachir Fradj; Benjamin Wolff; Normand Bélanger; Yvon Savaria (ISCAS, 2018)

Custom Low Power Processor for Polar Decoding. - Mathieu Léonardon; Camille Leroux; David Binet; J. M. Pierre Langlois; Christophe Jégo; Yvon Savaria (ISCAS, 2018)

A High-Efficiency Ultra-Low-Power CMOS Rectifier for RF Energy Harvesting Applications. - Seyed Mohammad Noghabaei; Rafael L. Radin; Yvon Savaria; Mohamad Sawan (ISCAS, 2018)

Transport Triggered Polar Decoders. - Mathieu Léonardon; Camille Leroux; Pekka Jääskeläinen; Christophe Jégo; Yvon Savaria (ISTC, 2018)

Local Queueing-Based Data-Driven Task Scheduling for Multicore Systems. - Meng Li 003; Chao Chen 031; Guchuan Zhu; Yvon Savaria (MWSCAS, 2018)

Extending a CPU Cache for Efficient IPv6 Lookup. - Benjamin Wolff; Bachir Fradj; Normand Bélanger; Yvon Savaria (MWSCAS, 2018)

HPQ: A High Capacity Hybrid Priority Queue Architecture for High-Speed Network Switches. - Imad Benacer; François-Raymond Boyer; Yvon Savaria (NEWCAS, 2018)

Exploiting built-in delay lines for applying launch-on-capture at-speed testing on self-timed circuits. - Omar Al-Terkawi Hasib; Daniel Crepeau; Thomas Awad; Andrei Dulipovici; Yvon Savaria; Claude Thibeault (VTS, 2018)

A Hybrid Architecture With Low Latency Interfaces Enabling Dynamic Cache Management. - Michel Gemieux; Meng Li 003; Yvon Savaria; Jean-Pierre David; Guchuan Zhu (IEEE Access, 2018)

New Insights Into Soft-Faults Induced Cardiac Pacemakers Malfunctions Analyzed at System-Level via Model Checking. - Ghaith Bany Hamad; Marwan Ammar; Otmane Aït Mohamed; Yvon Savaria (IEEE Access, 2018)

GaN Integration Technology, an Ideal Candidate for High-Temperature Applications: A Review. - Ahmad Hassan; Yvon Savaria; Mohamad Sawan (IEEE Access, 2018)

Formal Dependability Modeling and Optimization of Scrubbed-Partitioned TMR for SRAM-based FPGAs. - Khaza Anuarul Hoque; Otmane Aït Mohamed; Yvon Savaria (CoRR, 2018)

Enhanced Bloom filter utilisation scheme for string matching using a splitting approach. - Shervin Vakili; J. M. Pierre Langlois; Yvon Savaria; Naraig Manjikian (IET Commun., 2018)

Diagnosis algorithms for a reconfigurable and defect tolerant JTAG scan chain in large area integrated circuits. - Safa Berrima; Yves Blaquière; Yvon Savaria (Integr., 2018)

A pattern-based routing algorithm for a novel electronic system prototyping platform. - Etienne Lepercq; Yves Blaquière; Yvon Savaria (Integr., 2018)

Harvesting Energy From Aviation Data Lines: Implementation and Experimental Results. - Maryam Mohajertehrani; Yvon Savaria; Mohamad Sawan (IEEE Trans. Circuits Syst. I Regul. Pap., 2018)

A 1.5-pJ/bit, 9.04-Mbit/s Carrier-Width Demodulator for Data Transmission Over an Inductive Link Supporting Power and Data Transfer. - Aref Trigui; Mohamed Ali 001; Ahmed Chiheb Ammari; Yvon Savaria; Mohamad Sawan (IEEE Trans. Circuits Syst. II Express Briefs, 2018)

A Fast, Single-Instruction-Multiple-Data, Scalable Priority Queue. - Imad Benacer; François-Raymond Boyer; Yvon Savaria (IEEE Trans. Very Large Scale Integr. Syst., 2018)

Electronics and Packaging Intended for Emerging Harsh Environment Applications: A Review. - Ahmad Hassan; Yvon Savaria; Mohamad Sawan (IEEE Trans. Very Large Scale Integr. Syst., 2018)

Memristor Emulators for an Adaptive DPE Algorithm: Comparative Study. - Hussein Assaf; Yvon Savaria; Mohamad Sawan (AICAS, 2019)

AnARM: A 28nm Energy Efficient ARM Processor Based on Octasic Asynchronous Technology. - Mickaël Fiorentino; Claude Thibeault; Yvon Savaria; François Gagnon; Tom Awad; Doug Morrissey; Michel Laurence (ASYNC, 2019)

A Versatile SoC/SiP Sensor Interface for Industrial Applications: Design Considerations. - Mohamed Ali 001; Morteza Nabavi; Ahmad Hassan; Mohammad Honarparvar; Yvon Savaria; Mohamad Sawan (ICM, 2019)

Toward In-System Monitoring of OpenCL-Based Designs on FPGA. - Hachem Bensalem; Yves Blaquière; Yvon Savaria (ISCAS, 2019)

A Prediction Model for Implementing DVS in Single-Rail Bundled-Data Handshake-Free Asynchronous Circuits. - Maryem Benyoussef; Claude Thibeault; Yvon Savaria (ISCAS, 2019)

Bit-Slicing FPGA Accelerator for Quantized Neural Networks. - Olexa Bilaniuk; Sean Wagner; Yvon Savaria; Jean-Pierre David (ISCAS, 2019)

U-Net Fixed-Point Quantization for Medical Image Segmentation. - MohammadHossein AskariHemmat; Sina Honari; Lucas Rouhier; Christian S. Perone; Julien Cohen-Adad; Yvon Savaria; Jean-Pierre David (LABELS/HAL-MICCAI/CuRIOUS@MICCAI, 2019)

Towards an Accurate Probabilistic Modeling and Statistical Analysis of Temporal Faults via Temporal Dynamic Fault-Trees (TDFTs). - Marwan Ammar; Ghaith Bany Hamad; Otmane Aït Mohamed; Yvon Savaria (IEEE Access, 2019)

A High-Speed, Scalable, and Programmable Traffic Manager Architecture for Flow-Based Networking. - Imad Benacer; François-Raymond Boyer; Yvon Savaria (IEEE Access, 2019)

HPQS: A Fast, High-Capacity, Hybrid Priority Queuing System for High-Speed Networking Devices. - Imad Benacer; François-Raymond Boyer; Yvon Savaria (IEEE Access, 2019)

Toward High-Performance Implementation of 5G SCMA Algorithms. - Alireza Ghaffari; Mathieu Léonardon; Adrien Cassagne; Camille Leroux; Yvon Savaria (IEEE Access, 2019)

Energy Efficient Generic Demodulator for High Data Transmission Rate Over an Inductive Link for Implantable Devices. - Aref Trigui; Mohamed Ali 001; Ahmed Chiheb Ammari; Yvon Savaria; Mohamad Sawan (IEEE Access, 2019)

Multi-PVT-Point Analysis and Comparison of Recent Small-Delay Defect Quality Metrics. - Omar Al-Terkawi Hasib; Yvon Savaria; Claude Thibeault (J. Electron. Test., 2019)

GaN-based LSK demodulators for wireless data receivers in high-temperature applications. - Ahmad Hassan; Mohamed Ali 001; Yvon Savaria; Mohamad Sawan (Microelectron. J., 2019)

Dependability modeling and optimization of triple modular redundancy partitioning for SRAM-based FPGAs. - Khaza Anuarul Hoque; Otmane Aït Mohamed; Yvon Savaria (Reliab. Eng. Syst. Saf., 2019)

A GaN-Based Wireless Monitoring System for High-Temperature Applications. - Ahmad Hassan; Mohamed Ali 001; Aref Trigui; Yvon Savaria; Mohamad Sawan (Sensors, 2019)

SHIP: A Scalable High-Performance IPv6 Lookup Algorithm That Exploits Prefix Characteristics. - Thibaut Stimpfling; Normand Bélanger; J. M. Pierre Langlois; Yvon Savaria (IEEE/ACM Trans. Netw., 2019)

A Defect-Tolerant Reusable Network of DACs for Wafer-Scale Integration. - Nicolas Laflamme-Mayer; Gilbert Kowarzyk; Yves Blaquière; Yvon Savaria; Mohamad Sawan (IEEE Trans. Very Large Scale Integr. Syst., 2019)

Fast and Flexible Software Polar List Decoders. - Mathieu Léonardon; Adrien Cassagne; Camille Leroux; Christophe Jégo; Louis-Philippe Hamelin; Yvon Savaria (J. Signal Process. Syst., 2019)

On the Use of Interval Arithmetic for the Branch and Bound Delta-Lognormal Parameter Extraction of Rapid Human Movements. - Simon Pierre Boyogueno Bidias; Jean-Pierre David; Yvon Savaria; Réjean Plamondon (The Lognormality Principle, 2020)

Layerwise Noise Maximisation to Train Low-Energy Deep Neural Networks. - Sébastien Henwood; François Leduc-Primeau; Yvon Savaria (AICAS, 2020)

RISC-V Barrel Processor for Accelerator Control. - MohammadHossein AskariHemmat; Olexa Bilaniuk; Sean Wagner; Yvon Savaria; Jean-Pierre David (FCCM, 2020)

Unleashing the Power of FPGAs as Programmable Switches. - Thomas Luinaud; Thibaut Stimpfling; Jeferson Santiago da Silva; Yvon Savaria; J. M. Pierre Langlois (FPGA, 2020)

Bridging the Gap: FPGAs as Programmable Switches. - Thomas Luinaud; Thibaut Stimpfling; Jeferson Santiago da Silva; Yvon Savaria; J. M. Pierre Langlois (HPSR, 2020)

A 58 nW ± 35 ppm/°C Oscillator for IoT Battery-less Sensor Applications. - Milad Salehi; Mohamed Ali 001; Yvon Savaria; Mohamad Sawan (ICECS, 2020)

A VCO-Based Nonuniform Sampling ADC Using a Slope-Dependent Pulse Generator. - Mohamed Amine Bensenouci; Mohamed Ali 001; Hammoudi Escid; Yvon Savaria; Mohamad Sawan (ICM, 2020)

Self-Adjusting Deadtime Generator for High-Efficiency High-Voltage Switched-Mode Power Amplifiers. - Ahmed Abuelnasr; Mohamed Ali 001; Mostafa Amer; Morteza Nabavi; Ahmad Hassan; Benoit Gosselin; Yvon Savaria (ISCAS, 2020)

OTA-Free MASH 2-2 Noise Shaping SAR ADC: System and Design Considerations. - Masoume Akbari; Mohammad Honarparvar; Yvon Savaria; Mohamad Sawan (ISCAS, 2020)

Analog Circuits to Accelerate the Relaxation Process in the Equilibrium Propagation Algorithm. - Armin Najarpour Foroushani; Hussein Assaf; Fereidoon Hashemi Noshahr; Yvon Savaria; Mohamad Sawan (ISCAS, 2020)

A High Efficiency and Fast Response PLL Based Buck Converter: Implementation and Simulation. - Nader El-Zarif; Mohamed Ali 001; Ahmad Hassan; Morteza Nabavi; Christian Jesús B. Fayomi; Yvon Savaria (LASCAS, 2020)

SRAM Security and Vulnerability To Hardware Trojan: Design Considerations. - Roghayeh Saeidi; Morteza Nabavi; Yvon Savaria (MWSCAS, 2020)

OTA-Free MASH Two-Step Incremental ADC based on Noise Shaping SAR ADCs. - Masoume Akbari; Mohammad Honarparvar; Yvon Savaria; Mohamad Sawan (NEWCAS, 2020)

Fully Integrated Dual-Channel Gate Driver and Area Efficient PID Compensator for Surge Tolerant Power Sensor Interface. - Mostafa Amer; Mohamed Ali 001; Ahmed Abuelnasr; Ahmad Hassan; Morteza Nabavi; Yvon Savaria; Mohamad Sawan (NEWCAS, 2020)

Towards GaN500-based High Temperature ICs: Characterization and Modeling up to 600°C. - Ahmad Hassan; Mostafa Amer; Yvon Savaria; Mohamad Sawan (NEWCAS, 2020)

Indoor Localization Using Channel State Information With Regression Artificial Neural Networks. - Seyed Mohsen Samadani; Yvon Savaria; Chahé Nerguizian (VTC Spring, 2020)

In-FPGA Instrumentation Framework for OpenCL-Based Designs. - Hachem Bensalem; Yves Blaquière; Yvon Savaria (IEEE Access, 2020)

CNN2Gate: Toward Designing a General Framework for Implementation of Convolutional Neural Networks on FPGA. - Alireza Ghaffari; Yvon Savaria (CoRR, 2020)

Fine resolution delay tuning method to improve the linearity of an unbalanced time-to-digital converter on a Xilinx FPGA. - Safa Berrima; Yves Blaquière; Yvon Savaria (IET Circuits Devices Syst., 2020)

A Real-Time Thermal Monitoring System Intended for Embedded Sensors Interfaces. - Ouafaa Ettahri; Aziz Oukaira; Mohamed Ali 001; Ahmad Hassan; Morteza Nabavi; Yvon Savaria; Ahmed Lakhssassi (Sensors, 2020)

Fully Integrated Digital GaN-Based LSK Demodulator for High-Temperature Applications. - Ahmad Hassan; Mostafa Amer; Yvon Savaria; Mohamad Sawan (IEEE Trans. Circuits Syst. II Express Briefs, 2020)

Generic Wireless Power Transfer and Data Communication System Based on a Novel Modulation Technique. - Aref Trigui; Mohamed Ali 001; Sami Hached; Jean-Pierre David; Ahmed Chiheb Ammari; Yvon Savaria; Mohamad Sawan (IEEE Trans. Circuits Syst., 2020)

Desynchronized Model Predictive Control for Large Populations of Fans in Server Racks of Datacenters. - Gabriel Laparra; Meng Li 003; Guchuan Zhu; Yvon Savaria (IEEE Trans. Smart Grid, 2020)

Optimization of Small-Delay Defects Test Quality by Clock Speed Selection and Proper Masking Based on the Weighted Slack Percentage. - Omar Al-Terkawi Hasib; Yvon Savaria; Claude Thibeault (IEEE Trans. Very Large Scale Integr. Syst., 2020)

Human Activity Recognition and People Count for a SMART Public Transportation System. - Roya Alizadeh; Yvon Savaria; Chahé Nerguizian (5GWF, 2021)

Design Principles for Packet Deparsers on FPGAs. - Thomas Luinaud; Jeferson Santiago da Silva; J. M. Pierre Langlois; Yvon Savaria (FPGA, 2021)

Delay-Locked Loop Based Multiphase Clock Generator for Time-Interleaved ADCs. - Ibrahim Alhousseiny; Mohamed Ali 001; Naim Ben-Hamida; Mohammad Honarparvar; Mohamad Sawan; Yvon Savaria (ICECS, 2021)

Causal Information Prediction for Analog Circuit Design Using Variable Selection Methods Based on Machine Learning. - Ahmed Abuelnasr; Mostafa Amer; Ahmed Ragab; Benoit Gosselin; Yvon Savaria (ISCAS, 2021)

Design and Analysis of Combined Input-Voltage Feedforward and PI Controllers for the Buck Converter. - Mostafa Amer; Ahmed Abuelnasr; Ahmed Ragab; Ahmad Hassan; Mohamed Ali 001; Benoit Gosselin; Mohamad Sawan; Yvon Savaria (ISCAS, 2021)

RISC-V Barrel Processor for Deep Neural Network Acceleration. - MohammadHossein AskariHemmat; Olexa Bilaniuk; Sean Wagner; Yvon Savaria; Jean-Pierre David (ISCAS, 2021)

Acceleration of the Secure Hash Algorithm-256 (SHA-256) on an FPGA-CPU Cluster Using OpenCL. - Hachem Bensalem; Yves Blaquière; Yvon Savaria (ISCAS, 2021)

Thermo-mechanical Analysis and Fatigue Life Prediction for Integrated Circuits (ICs). - Aziz Oukaira; Touati Djallel eddine; Ahmad Hassan; Mohamed Ali 001; Yvon Savaria; Ahmed Lakhssassi (MWSCAS, 2021)

Non-parametric Statistical Static Timing Analysis based on Improved Parallel Monte Carlo. - Zahra Qavamy; Behnam Ghavami; Morteza Nabavi; Yvon Savaria (MWSCAS, 2021)

Foster-based Transient Thermal Analysis of SiP for Thermomechanical Studies. - Touati Djallel eddine; Aziz Oukaira; Ahmad Hassan; Yvon Savaria; Ahmed Lakhssassi (NEWCAS, 2021)

Efficient Design Space Exploration of OpenCL Kernels for FPGA Targets Using Black Box Optimization. - Alireza Ghaffari; Yvon Savaria (IEEE Access, 2021)

Introducing KeyRing self-timed microarchitecture and timing-driven design flow. - Mickaël Fiorentino; Claude Thibeault; Yvon Savaria (IET Comput. Digit. Tech., 2021)

Power Bound Analysis of a Two-Step MASH Incremental ADC Based on Noise-Shaping SAR ADCs. - Masoume Akbari; Mohammad Honarparvar; Yvon Savaria; Mohamad Sawan (IEEE Trans. Circuits Syst. I Regul. Pap., 2021)

Ring-Oscillator-Based High Accuracy Low Complexity Multichannel Time-to-Digital Converter Architecture for Field-Programmable Gate Arrays. - Safa Berrima; Yves Blaquière; Yvon Savaria (IEEE Trans. Instrum. Meas., 2021)

Multi-Sensor Track-to-Track Association and Spatial Registration Algorithm Under Incomplete Measurements. - Jun Wang 041; Yajun Zeng; Shaoming Wei; Zixiang Wei; Qinchen Wu; Yvon Savaria (IEEE Trans. Signal Process., 2021)

MemSE: Fast MSE Prediction for Noisy Memristor-Based DNN Accelerators. - Jonathan Kern; Sébastien Henwood; Gonçalo Mordido; Elsa Dupraz; Abdeldjalil Aïssa-El-Bey; Yvon Savaria; François Leduc-Primeau (AICAS, 2022)

Tiny CNN for Seizure Prediction in Wearable Biomedical Devices. - Yang Zhang; Yvon Savaria; Shiqi Zhao; Gonçalo Mordido; Mohamad Sawan; François Leduc-Primeau (EMBC, 2022)

Automatic Detection of People Getting Into a Bus in a SMART Public Transportation System. - Roya Alizadeh; Yvon Savaria; Chahé Nerguizian (ICECS 2022, 2022)

A Templated VHDL Architecture for Terabit/s P4-programmable FPGA-based Packet Parsing. - Parisa Mashreghi-Moghadam; Tarek Ould-Bachir; Yvon Savaria (ISCAS, 2022)

Mobile-URSONet: an Embeddable Neural Network for Onboard Spacecraft Pose Estimation. - Julien Posso; Guy Bois; Yvon Savaria (ISCAS, 2022)

An FPGA-based HW/SW Co-Verification Environment for Programmable Network Devices. - Mengyue Su; Jean-Pierre David; Yvon Savaria; Bill Pontikakis; Thomas Luinaud (ISCAS, 2022)

Low Complexity Shallow Neural Network With Improved False Negative Rate for Cyber Intrusion Detection Systems. - Jörg Ehmer; Bertrand Granado; Julien Denoulet; Yvon Savaria; Jean-Pierre David (NEWCAS, 2022)

Investigation of Different Integrated Temperature Monitoring Sensors for High-Voltage SoC DC-DC Converters. - Nader El-Zarif; Mohamed Ali 001; Mostafa Amer; Ahmad Hassan; Aziz Oukaira; Ahmed Lakhssassi; Christian Jesús B. Fayomi; Yvon Savaria (NEWCAS, 2022)

RLBEEP: Reinforcement-Learning-Based Energy Efficient Control and Routing Protocol for Wireless Sensor Networks. - Ali Forghani Elah Abadi; Seyyed Amir Asghari; Mohammadreza Binesh Marvasti; Golnoush Abaei; Morteza Nabavi; Yvon Savaria (IEEE Access, 2022)

A Versatile SoC/SiP Sensor Interface for Industrial Applications: Implementation Challenges. - Mohamed Ali 001; Ahmad Hassan; Mohammad Honarparvar; Morteza Nabavi; Yves Audet; Mohamad Sawan; Yvon Savaria (IEEE Access, 2022)

A Hybrid Approach Based on Recurrent Neural Network for Macromodeling of Nonlinear Electronic Circuits. - Amin Faraji; Sayed Alireza Sadrossadat; Mahdi Yazdian Dehkordi; Morteza Nabavi; Yvon Savaria (IEEE Access, 2022)

IBU: An In-Block Update Address Mapping Scheme for Solid-State Drives. - Reza Gholami Taghizadeh; Mohammadreza Binesh Marvasti; Seyyed Amir Asghari; Ramin Gholami Taghizadeh; Morteza Nabavi; Yvon Savaria (IEEE Access, 2022)

Rethinking Pareto Frontier for Performance Evaluation of Deep Neural Networks. - Vahid Partovi Nia; Alireza Ghaffari; Mahdi Zolnouri; Yvon Savaria (CoRR, 2022)

QReg: On Regularization Effects of Quantization. - MohammadHossein AskariHemmat; Reyhane Askari Hemmat; Alexander Hoffman; Ivan Lazarevich; Ehsan Saboori; Olivier Mastropietro; Yvon Savaria; Jean-Pierre David (CoRR, 2022)

Persistence Region Monitor With a Pheromone-Inspired Robot Swarm Sensor Network. - Yuzhan Wu; Meng Li 003; Guannan Li; Yvon Savaria (IEEE Internet Things J., 2022)

Towards Real-Time Monitoring of Thermal Peaks in Systems-on-Chip (SoC). - Aziz Oukaira; Ahmad Hassan; Mohamed Ali 001; Yvon Savaria; Ahmed Lakhssassi (Sensors, 2022)

A Molecular Imprinted PEDOT CMOS Chip-Based Biosensor for Carbamazepine Detection. - Abbas Hammoud; Hussein Assaf; Yvon Savaria; Dang Khoa Nguyen; Mohamad Sawan (IEEE Trans. Biomed. Circuits Syst., 2022)

A High-Sensitivity Wide Input-Power-Range Ultra-Low-Power RF Energy Harvester for IoT Applications. - Seyed Mohammad Noghabaei; Rafael L. Radin; Yvon Savaria; Mohamad Sawan (IEEE Trans. Circuits Syst. I Regul. Pap., 2022)

BARVINN: Arbitrary Precision DNN Accelerator Controlled by a RISC-V CPU. - Mohammadhossein Askarihemmat; Sean Wagner; Olexa Bilaniuk; Yassine Hariri; Yvon Savaria; Jean-Pierre David (ASP-DAC, 2023)

Implementing and Evaluating a P4-based Access Gateway Function on a Tofino Switch. - El-Mehdi Makhroute; Mohammed-Ayoub Elharti; Vincent Brouillard; Yvon Savaria; Tarek Ould-Bachir (CommNet, 2023)

Enabling Human Activity Recognition in Smart Public Transportation Systems in Presence of Dataset Imbalance. - Roya Alizadeh; Yvon Savaria; Chahé Nerguizian (ICECS, 2023)

Quark: An Integer RISC-V Vector Processor for Sub-Byte Quantized DNN Inference. - MohammadHossein AskariHemmat; Théo Dupuis; Yoan Fournier; Nizar El Zarif; Matheus A. Cavalcante; Matteo Perotti; Frank K. Gürkaynak; Luca Benini; François Leduc-Primeau; Yvon Savaria; Jean-Pierre David (ISCAS, 2023)

An Area-efficient Memory-based Architecture for P4-programmable Streaming Parsers in FPGAs. - Parisa Mashreghi-Moghadam; Tarek Ould-Bachir; Yvon Savaria (ISCAS, 2023)

Sparq: A Custom RISC-V Vector Processor for Efficient Sub-Byte Quantized Inference. - Théo Dupuis; Yoan Fournier; MohammadHossein AskariHemmat; Nizar El Zarif; François Leduc-Primeau; Jean-Pierre David; Yvon Savaria (NEWCAS, 2023)

Low-Energy, Scalable, On-demand State-of-charge Estimation System for Li-ion batteries. - Dufour Jules; Yvon Savaria; Jean-Pierre David (NEWCAS, 2023)

Background Calibration of Time-Interleaved ADCs with Polyphase Filters. - Hamidreza Mafi; Mohamed Ali 001; Yvon Savaria; Mohammad Honarparvar; Naim Ben-Hamida (NEWCAS, 2023)

High-Temperature Fully Integrated Wireless Monitoring Systems for Aerospace Applications. - Ahmad Hassan; Aref Trigui; Yvon Savaria; Mohamad Sawan (WiSEE, 2023)

A Hardware Architecture of a Dynamic Ranking Packet Scheduler for Programmable Network Devices. - Mostafa Elbediwy; Bill Pontikakis; Jean-Pierre David; Yvon Savaria (IEEE Access, 2023)

Enhanced Artificial Vision for Visually Impaired Using Visual Implants. - Hossein Mahvash Mohammadi; Mohammad Hadi Edrisi; Yvon Savaria (IEEE Access, 2023)

Statistical Hardware Design With Multi-model Active Learning. - Alireza Ghaffari; Masoud Asgharian; Yvon Savaria (CoRR, 2023)

Symbolic Analysis for Data Plane Programs Specialization. - Thomas Luinaud; J. M. Pierre Langlois; Yvon Savaria (ACM Trans. Archit. Code Optim., 2023)

An Efficient OpenCL-Based Implementation of a SHA-3 Co-Processor on an FPGA-Centric Platform. - Hachem Bensalem; Yves Blaquière; Yvon Savaria (IEEE Trans. Circuits Syst. II Express Briefs, 2023)

Delay Mismatch Insensitive Dead Time Generator for High-Voltage Switched-Mode Power Amplifiers. - Ahmed Abuelnasr; Mostafa Amer; Mohamed Ali 001; Ahmad Hassan; Benoit Gosselin; Ahmed Ragab; Yvon Savaria (IEEE Trans. Circuits Syst. I Regul. Pap., 2023)

Sharpness-Aware Minimization Scaled by Outlier Normalization for Robust DNNs on In-Memory Computing Accelerators. - Sébastien Henwood; Gonçalo Mordido; Yvon Savaria; Sarath Chandar; François Leduc-Primeau (IEEECONF, 2024)

Normal and Resilient Mode FPGA-based Access Gateway Function Through P4-generated RTL. - Mostafa Abbasmollaei; Tarek Ould-Bachir; Yvon Savaria (DRCN, 2024)

Utilization of Noise-Shaping in Mixed-Signal Timing-Skew Mismatch Calibration of TI-ADCs. - Hamidreza Mafi; Mohamed Amine Bensenouci; Sadok Aouini; Mohammad Honarparvar; Naim Ben-Hamida; Yvon Savaria (ISCAS, 2024)

MSPARQ: A RISC-V Vector Processor Array Optimized for Low-Resolution Neural Networks. - Elisabeth Humblet; Théo Dupuis; Yoan Fournier; MohammadHossein AskariHemmat; François Leduc-Primeau; Jean-Pierre David; Yvon Savaria (MWSCAS, 2024)

Enhancing P4 Syntax to Support Extended Finite State Machines as Native Stateful Objects. - Florent Allard; Tarek Ould-Bachir; Yvon Savaria (NetSoft, 2024)

A Flexible Thermal/Solar Energy Harvesting System with Hysteretic Control and Maximum Power Point Tracking Regulation for IoT Devices. - Karim Kaced; Sebastien Genevey; Yvon Savaria; Jean-Pierre David (NewCAS, 2024)

Digital Compensation of Timing-Skew Mismatches in TI-ADCs by Modulation and Source Separation. - Hamidreza Mafi; Naim Ben-Hamida; Sadok Aouini; Yvon Savaria (NewCAS, 2024)

CoChrono: A Unified Hardware/Software Performance Analysis Tool for SoC-FPGA Codesign. - Fabien Portas; Guy Bois; Yvon Savaria (NewCAS, 2024)

Real-Time Spacecraft Pose Estimation Using Mixed-Precision Quantized Neural Network on COTS Reconfigurable MPSoC. - Julien Posso; Guy Bois; Yvon Savaria (NewCAS, 2024)

$ mathcal{S}^{3}$1DCNN: A Compact Stacked Spectral-Spatial Attention 1DCNN for Seizure Prediction with Wearables. - Yang Zhang; Yvon Savaria; Mohamad Sawan; François Leduc-Primeau (NewCAS, 2024)

MemNAS: Super-net Neural Architecture Search for Memristor-based DNN Accelerators. - Sébastien Henwood; Yvon Savaria; François Leduc-Primeau (SiPS, 2024)

Recent Start-Up Techniques Intended for TEG Energy Harvesting: A Review. - Mahmoud Ahmed; Sebastien Genevey; Mohamed Ali 001; Yvon Savaria; Yves Audet (IEEE Access, 2024)

A 32-mV Supply Ring Oscillator Composed of Modified Schmitt Trigger Delay Cells for Integrated Start-Up Circuits in DC Energy Harvesting Systems. - Mahmoud Ahmed; Aref Trigui; Sebastien Genevey; Yves Audet; Yvon Savaria (IEEE Access, 2024)

Enhanced Dynamic Regulation in Buck Converters: Integrating Input-Voltage Feedforward With Voltage-Mode Feedback. - Mostafa Amer; Ahmed Abuelnasr; Mohamed Ali 001; Ahmad Hassan; Aref Trigui; Ahmed Ragab; Mohamad Sawan; Yvon Savaria (IEEE Access, 2024)

Nonlinear Circuit Macromodeling Using New Heterogeneous-Layered Deep Clockwork Recurrent Neural Network. - Maedeh Azodi; Sayed Alireza Sadrossadat; Yvon Savaria (IEEE Access, 2024)

A Systematic Approach for PLL-Based Zeta Power Converter Control. - Nader El-Zarif; Christian Jesús B. Fayomi; Mohamed Ali 001; Mostafa Amer; Ahmad Hassan; Yvon Savaria (IEEE Access, 2024)

Novel Peak-Source-Scanning (NPSS) Model for Thermal Control of Systems-in-Package (SiP). - Aziz Oukaira; Dhaou Said; Touati Djallel eddine; Nader El-Zarif; Ahmad Hassan; Yvon Savaria; Ahmed Lakhssassi (IEEE Access, 2024)

Polara-Keras2c: Supporting Vectorized AI Models on RISC-V Edge Devices. - Nizar El Zarif; MohammadHossein AskariHemmat; Théo Dupuis; Jean-Pierre David; Yvon Savaria (IEEE Access, 2024)

QGen: On the Ability to Generalize in Quantization Aware Training. - MohammadHossein AskariHemmat; Ahmadreza Jeddi; Reyhane Askari Hemmat; Ivan Lazarevich; Alexander Hoffman; Sudhakar Sah; Ehsan Saboori; Yvon Savaria; Jean-Pierre David (CoRR, 2024)

Incremental reinforcement learning for multi-objective analog circuit design acceleration. - Ahmed Abuelnasr; Ahmed Ragab; Mostafa Amer; Benoit Gosselin; Yvon Savaria (Eng. Appl. Artif. Intell., 2024)

Digital Compensation of Timing Skew Mismatches in Time-Interleaved ADCs by Source Separation. - Hamidreza Mafi; Naim Ben-Hamida; Sadok Aouini; Yvon Savaria (IEEE Trans. Instrum. Meas., 2024)

Fast and Accurate Output Error Estimation for Memristor-Based Deep Neural Networks. - Jonathan Kern; Sébastien Henwood; Gonçalo Mordido; Elsa Dupraz; Abdeldjalil Aïssa-El-Bey; Yvon Savaria; François Leduc-Primeau (IEEE Trans. Signal Process., 2024)

Spatial Registration of Heterogeneous Sensors on Mobile Platforms. - Yajun Zeng; Jun Wang 041; Shaoming Wei; Jinping Sun; Peng Lei; Yvon Savaria; Chi Zhang (IEEE Trans. Signal Process., 2024)

Calibration of Ring Oscillator-Based Integrated Temperature Sensors for Power Management Systems. - Nader El-Zarif; Mostafa Amer; Mohamed Ali 001; Ahmad Hassan; Aziz Oukaira; Christian Jesús B. Fayomi; Yvon Savaria (Sensors, 2024)

Statistical Hardware Design With Multimodel Active Learning. - Alireza Ghaffari; Masoud Asgharian; Yvon Savaria (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2024)

DR-PIFO: A Dynamic Ranking Packet Scheduler Using a Push-In-First-Out Queue. - Mostafa Elbediwy; Bill Pontikakis; Alireza Ghaffari; Jean-Pierre David; Yvon Savaria (IEEE Trans. Netw. Serv. Manag., 2024)

PrismParser: A Framework for Implementing Efficient P4-Programmable Packet Parsers on FPGA. - Parisa Mashreghi-Moghadam; Tarek Ould-Bachir; Yvon Savaria (Future Internet, 2024)

A Comparative Analysis of Off-Policy DRL Strategies for Analog Circuit Optimization: A Case Study on Bandgap References. - Muhammed Abdelfatah; Ahmed Abuelnasr; Mostafa Amer; Yvon Savaria; Ahmad Hassan (NewCAS, 2025)

Long Short-Term Memory Neural Network Combined With a Hybrid-Modular Clockwork Structure for Transient Modeling of Nonlinear Circuits. - Razieh Moradi Chaleshtori; Amin Saboohi; Amin Faraji; Sayed Alireza Sadrossadat; Ali Moftakharzadeh; Yvon Savaria (IEEE Access, 2025)

5G Fronthaul in Modular P4: eCPRI Protocol Processing and Precise BMv2 Timestamps for PTP-1588. - Atabak Nojavan; Bill Pontikakis; François-Raymond Boyer; Yvon Savaria (IEEE Access, 2025)

P4Muse: Enabling Modular P4 Programming via Compiler-Managed Code Merging Without Syntax Modifications. - Mohsen Rahmati; François-Raymond Boyer; Bill Pontikakis; Jean-Pierre David; Yvon Savaria (IEEE Access, 2025)

Thermal Analysis of System in Package Considering Boundary Conditions for Long-Term Reliability Studies. - Touati Djallel eddine; Aziz Oukaira; Ahmad Hassan; Mohamed Ali 001; Yvon Savaria; Ahmed Lakhssassi (IEEE Access, 2025)