Towards Designing Asynchronous Microprocessors: From Specification to Tape-Out. - Zaheer Tabassam; Syed Rameez Naqvi; Tallha Akram; Musaed A. Alhussein; Khursheed Aurangzeb; Sajjad Ali Haider (IEEE Access, 2019)

Towards Explaining the Fault Sensitivity of Different QDI Pipeline Styles. - Patrick Behal; Florian Huemer; Robert Najvirt; Andreas Steininger; Zaheer Tabassam (ASYNC, 2021)

AµFLIPS: An Asynchronous Microprocessor With FLexIbly-timed Pipeline Stages. - Zaheer Tabassam; Syed Rameez Naqvi; Andreas Steininger (DDECS, 2022)

SET Hardened Derivatives of QDI Buffer Template. - Zaheer Tabassam; Andreas Steininger (DFT, 2022)

Towards Resilient QDI Pipeline Implementations. - Zaheer Tabassam; Andreas Steininger (DSD, 2022)

ζ: A Novel Approach for Mitigating Single Event Transient Effects in Quasi Delay Insensitive Logic. - Zaheer Tabassam; Andreas Steininger; Robert Najvirt; Florian Huemer (ASYNC, 2023)

Towards Resilient Quasi Delay Insensitive Conditional Control Elements. - Zaheer Tabassam; Andreas Steininger (DSD, 2023)

SET Effects on Quasi Delay Insensitive and Synchronous Circuits. - Zaheer Tabassam; Andreas Steininger (ETS, 2023)