Memory-Less Pipeline Dynamic Circuit Design Technique. - Themistoklis Haniotakis; Zaher Owda; Yiorgos Tsiatouhas (ISVLSI, 2010)

New High-Speed Multioutput Carry Look-Ahead Adders. - Costas Efstathiou; Zaher Owda; Yiorgos Tsiatouhas (IEEE Trans. Circuits Syst. II Express Briefs, 2013)

End-to-End Real-Time Communication in Mixed-Criticality Systems Based on Networked Multicore Chips. - Roman Obermaisser; Zaher Owda; Mohammed Abuteir; Hamidreza Ahmadian; Donatus Weber (DSD, 2014)

Predictable and reliable time triggered platform for Ambient Assisted Living. - Zaher Owda; Mohammed Abuteir; Roman Obermaisser; Hamzah Dakheel (ISMICT, 2014)

Simulation Environment Based on SystemC and VEOS for Multi-core Processors with Virtual AUTOSAR ECUs. - Moisés Urbina; Zaher Owda; Roman Obermaisser (CIT/IUCC/DASC/PICom, 2015)

Off-Chip/On-chip Gateway Architecture for Mixed-Criticality Systems Based on Networked Multi-core Chips. - Mohammed Abuteir; Roman Obermaisser; Zaher Owda; Thierry Moudouthe (CSE, 2015)

Trace-based simulation framework combining message-based and shared-memory interactions in a time-triggered platform. - Zaher Owda; Roman Obermaisser (EBCCSP, 2015)

Co-simulation framework for networked multi-core chips with interleaving discrete event simulation tools. - Zaher Owda; Mohammed Abuteir; Roman Obermaisser (ETFA, 2015)

A Predictable Transactional Memory Architecture with Selective Conflict Resolution for Mixed-Criticality Support in MPSoCs. - Zaher Owda; Roman Obermaisser (EUC, 2015)

On-chip networks for mixed-criticality systems. - Polydoros Petrakis; Mohammed Abuteir; Miltos D. Grammatikakis; Kyprianos Papadimitriou; Roman Obermaisser; Zaher Owda; Antonis Papagrigoriou; Michael Soulie; Marcello Coppola (ASAP, 2016)

Hierarchical Transactional Memory Protocol for Distributed Mixed-Criticality Embedded Systems. - Zaher Owda; Moisés Urbina; Roman Obermaisser; Mohammed Abuteir (DASC/PiCom/DataCom/CyberSciTech, 2016)

Mixed-criticality transactional memory controller for embedded systems. - Zaher Owda; Roman Obermaisser (INDIN, 2016)

Predictable transactional memory architecture for hierarchical mixed-criticality systems. - Zaher Owda (2017)

Simulation Model and Environment for Mixed-Criticality Networked Multi-Core Chips. - Mohammed Abuteir; Zaher Owda; Hamidreza Ahmadian; Roman Obermaisser (SIES, 2018)