Secure by construction: addressing security vulnerabilities introduced during high-level synthesis: invited. - Md Rafid Muttaki; Zahin Ibnat; Farimah Farahmandi (DAC, 2022)

ActiWate: Adaptive and Design-agnostic Active Watermarking for IP Ownership in Modern SoCs. - Zahin Ibnat; M. Sazadur Rahman; Mridha Md Mashahedur Rahman; Hadi Mardani Kamali; Mark Tehranipoor; Farimah Farahmandi (DAC, 2023)

Iterative Mitigation of Insecure Resource Sharing Produced by High-level Synthesis. - Zahin Ibnat; Hadi Mardani Kamali; Farimah Farahmandi (DFT, 2023)

Security of Hardware Generators: Enabling Assurance in High-Level Synthesis. - Md Rafid Muttaki; Zahin Ibnat; Shang Shi; Hadi Mardani Kamali; Farimah Farahmandi (MWSCAS, 2023)

VerilogDB: The Largest, Highest-Quality Dataset with a Preprocessing Framework for LLM-based RTL Generation. - Paul Calzada; Zahin Ibnat; Tanvir Rahman; Kamal Kandula; Danyu Lu; Sujan Kumar Saha; Farimah Farahmandi; Mark Tehranipoor (CoRR, 2025)