An Efficient Protection Technique for Last Level STT-RAM Caches in Multi-Core Processors. - Zahra Azad; Hamed Farbeh; Amir Mahdi Hosseini Monazzah; Seyed Ghassem Miremadi (IEEE Trans. Parallel Distributed Syst., 2017)

ORIENT: Organized interleaved ECCs for new STT-MRAM caches. - Zahra Azad; Hamed Farbeh; Amir Mahdi Hosseini Monazzah (DATE, 2018)

AWARE: Adaptive Way Allocation for Reconfigurable ECCs to Protect Write Errors in STT-RAM Caches. - Zahra Azad; Hamed Farbeh; Amir Mahdi Hosseini Monazzah; Seyed Ghassem Miremadi (IEEE Trans. Emerg. Top. Comput., 2019)

BlackParrot: An Agile Open-Source RISC-V Multicore for Accelerator SoCs. - Daniel Petrisko; Farzam Gilani; Mark Wyse; Dai Cheol Jung; Scott Davidson 004; Paul Gao 001; Chun Zhao; Zahra Azad; Sadullah Canakci; Bandhav Veluri; Tavio Guarino; Ajay Joshi; et al. (IEEE Micro, 2020)

Hardware Acceleration for DBMS Machine Learning Scoring: Is It Worth the Overheads? - Zahra Azad; Rathijit Sen; Kwanghyun Park 001; Ajay Joshi (ISPASS, 2021)

AI Tax in Mobile SoCs: End-to-end Performance Analysis of Machine Learning in Smartphones. - Michael Buch; Zahra Azad; Ajay Joshi; Vijay Janapa Reddi (ISPASS, 2021)

RACE: RISC-V SoC for En/decryption Acceleration on the Edge for Homomorphic Computation. - Zahra Azad; Guowei Yang 005; Rashmi Agrawal 001; Daniel Petrisko; Michael B. Taylor; Ajay Joshi (ISLPED, 2022)

RISE: RISC-V SoC for En/Decryption Acceleration on the Edge for Homomorphic Encryption. - Zahra Azad; Guowei Yang 005; Rashmi Agrawal 001; Daniel Petrisko; Michael Bedford Taylor; Ajay Joshi (IEEE Trans. Very Large Scale Integr. Syst., 2023)

Bridging the Gap Between LLMs and LNS with Dynamic Data Format and Architecture Codesign. - Pouya Haghi; Chunshu Wu; Zahra Azad; Yanfei Li; Andrew Gui; Yuchen Hao; Ang Li 006; Tony Tong Geng (MICRO, 2024)