A novel hybrid FIFO asynchronous clock domain crossing interfacing method. - Zaid Al-bayati; Otmane Aït Mohamed; Syed Rafay Hasan; Yvon Savaria (ACM Great Lakes Symposium on VLSI, 2012)

Probabilistic model checking of clock domain crossing interfaces. - Zaid Al-bayati; Otmane Aït Mohamed; Yvon Savaria; Mounir Boukadoum (NEWCAS, 2012)

Low power Wallace multiplier design based on wide counters. - Sa'ed Abed; Bassam Jamil Mohd; Zaid Al-bayati; Sahel Alouneh (Int. J. Circuit Theory Appl., 2012)

Multitask implementation of synchronous reactive models with Earliest Deadline First scheduling. - Zaid Al-bayati; Haibo Zeng 001; Marco Di Natale; Zonghua Gu 001 (SIES, 2013)

Enhanced partitioned scheduling of Mixed-Criticality Systems on multicore platforms. - Zaid Al-bayati; Qingling Zhao; Ahmed Youssef; Haibo Zeng 001; Zonghua Gu 001 (ASP-DAC, 2015)

Task placement and selection of data consistency mechanisms for real-time multicore applications. - Zaid Al-bayati; Youcheng Sun; Haibo Zeng 001; Marco Di Natale; Qi Zhu 002; Brett H. Meyer (RTAS, 2015)

A four-mode model for efficient fault-tolerant mixed-criticality systems. - Zaid Al-bayati; Jonah Caplan; Brett H. Meyer; Haibo Zeng 001 (DATE, 2016)

Fault-tolerant scheduling of multicore mixed-criticality systems under permanent failures. - Zaid Al-bayati; Brett H. Meyer; Haibo Zeng 001 (DFT, 2016)

Optimized Implementation of Multirate Mixed-Criticality Synchronous Reactive Models. - Qingling Zhao; Zaid Al-bayati; Zonghua Gu 001; Haibo Zeng 001 (ACM Trans. Design Autom. Electr. Syst., 2017)

Mapping and Scheduling Mixed-Criticality Systems with On-Demand Redundancy. - Jonah Caplan; Zaid Al-bayati; Haibo Zeng 001; Brett H. Meyer (IEEE Trans. Computers, 2018)

Partitioning and Selection of Data Consistency Mechanisms for Multicore Real-Time Systems. - Zaid Al-bayati; Youcheng Sun; Haibo Zeng 001; Marco Di Natale; Qi Zhu 002; Brett H. Meyer (ACM Trans. Embed. Comput. Syst., 2019)