Towards Line-Aware Realizations of Expressions for HDL-Based Synthesis of Reversible Circuits. - Zaid Al-Wardi; Robert Wille; Rolf Drechsler (RC, 2015)

Re-Writing HDL Descriptions for Line-Aware Synthesis of Reversible Circuits. - Zaid Al-Wardi; Robert Wille; Rolf Drechsler (ISMVL, 2016)

Extensions to the Reversible Hardware Description Language SyReC. - Zaid Al-Wardi; Robert Wille; Rolf Drechsler (ISMVL, 2017)

Towards VHDL-Based Design of Reversible Circuits - Work in Progress Report. - Zaid Al-Wardi; Robert Wille; Rolf Drechsler (RC, 2017)

Synthesis of Reversible Circuits Using Conventional Hardware Description Languages. - Zaid Al-Wardi; Robert Wille; Rolf Drechsler (ISMVL, 2018)