A neural network algorithm for testing stuck-open faults in CMOS combinational circuits. - Zaifu Zhang; Robert D. McLeod; Witold Pedrycz (J. Electron. Test., 1993)

Augmenting Scan Path SRLs with an XOR Network to Enhance Delay Fault Testing. - Zaifu Zhang; Robert D. McLeod; Witold Pedrycz (DFT, 1994)

Simulating Static and Dynamic Faults in BIST Strucutres with a FPGA Based Emulator. - Richard W. Wieler; Zaifu Zhang; Robert D. McLeod (FPL, 1994)

Using an FPGA based computer as a hardware emulator for built-in self-test structures. - Richard W. Wieler; Zaifu Zhang; Robert D. McLeod (RSP, 1994)

Emulating static faults using a Xilinx based emulator. - Richard W. Wieler; Zaifu Zhang; Robert D. McLeod (FCCM, 1995)

An Efficient Multiple Scan Chain Testing Scheme. - Zaifu Zhang; Robert D. McLeod (Great Lakes Symposium on VLSI, 1996)

Statistical estimation of delay fault detectabilities and fault grading. - Zaifu Zhang; Robert D. McLeod; Gregory E. Bridges (J. Electron. Test., 1996)