Energy efficient approximate booth multipliers using compact error compensation circuit for mitigation of truncation error. - Zainab Aizaz; Kavita Khare (Int. J. Circuit Theory Appl., 2022)

Area and Power Efficient Truncated Booth Multipliers Using Approximate Carry-Based Error Compensation. - Zainab Aizaz; Kavita Khare (IEEE Trans. Circuits Syst. II Express Briefs, 2022)

A1RL: Approximate 1-Row-LUT-Based Low-Power Signed Multipliers for DSP and Machine Learning Applications on FPGAs. - Zainab Aizaz; Kavita Khare; Mohd Anas Khan; Mahesh Kumar Singh; Vaithiyanathan Dhandapani (APCCAS, 2023)

FASBM: FPGA-specific Approximate Sum-based Booth multipliers for energy efficient Hardware Acceleration of Image Processing and Machine Learning Applications. - Zainab Aizaz; Kavita Khare; Aizaz Tirmizi (FCCM, 2023)

ASMPEC: Approximate-Sum-Based Mapping of Partial Products With Error Correction for Softcore Multipliers on FPGAs. - Zainab Aizaz; Kavita Khare (IEEE Trans. Circuits Syst. II Express Briefs, 2023)

Approximate Row-Merging-Based Multipliers for Neural Network Acceleration on FPGAs. - Zainab Aizaz; Kavita Khare; Aizaz Tirmizi (IEEE Embed. Syst. Lett., 2024)

FeNN: A RISC-V vector processor for Spiking Neural Network acceleration. - Zainab Aizaz; James C. Knight; Thomas Nowotny (NICE, 2025)