Efficient simulation of AHPL. - Zainalabedin Navabi; Fredrick J. Hill (DAC, 1979)

Structure Specification with a Procedural Hardware Description Language. - Fredrick J. Hill; R. E. Swanson; Manzer Masud; Zainalabedin Navabi (IEEE Trans. Computers, 1981)

Hardware Compilation from an RTL to a Storage Logic Array Target. - Fredrick J. Hill; Zainalabedin Navabi; Chen H. Chiang; Duan-Ping Chen; Manzer Masud (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1984)

Compiling gate RC models into a top level simulation model for rough timing analysis of VLSI circuits. - Zainalabedin Navabi (Microprocess. Microsystems, 1991)

Investigating simulation of hardware at various levels of abstraction and timing back-annotation of dataflow descriptions. - Zainalabedin Navabi; Mehran Massoumi (Simul., 1991)

A high-level language for design and modeling of hardware. - Zainalabedin Navabi (J. Syst. Softw., 1992)

Modeling Timing Behavior of Logic Circuits Using Piecewise Linear Models. - Zainalabedin Navabi; Amirhooshang Hashemi; Massoud Eghtesad; Mankuan Michael Vai (CHDL, 1993)

A Transistor Level Link for VHDL Simulation of VLSI Circuits. - Zainalabedin Navabi; Zahra Razavi (Simul., 1995)

Hardware Description in Verilog. - Zainalabedin Navabi (The VLSI Handbook, 1999)

Fault Simulation for VHDL Based Test Bench and BIST Evaluation. - Hamed Farshbaf; Mina Zolfy; Shahrzad Mirkhani; Zainalabedin Navabi (Asian Test Symposium, 2001)

Adaptation of an event-driven simulation environment to sequentially propagated concurrent fault simulation. - Mina Zolfy; Shahrzad Mirkhani; Zainalabedin Navabi (DATE, 2001)

An efficient BIST method for testing of embedded SRAMs. - Mohammad H. Tehranipour; Zainalabedin Navabi; Seid Mehdi Fakhraie (ISCAS (5), 2001)

Hierarchical Fault Simulation Using Behavioral and Gate Level Hardware Models. - Shahrzad Mirkhani; Meisam Lavasani; Zainalabedin Navabi (Asian Test Symposium, 2002)

Data Compression for System-on-Chip Testing Using ATE. - Farzin Karimi; Waleed Meleis; Zainalabedin Navabi; Fabrizio Lombardi (DFT, 2002)

A BIST Architecture for FPGA Look-Up Table Testing Reduces Reconfigurations. - Ehsan Atoofian; Zainalabedin Navabi (Asian Test Symposium, 2003)

The VPI-Based Combinational IP Core Module-Based Mixed Level Serial Fault Simulation and Test Generation Methodology. - Pedram A. Riahi; Zainalabedin Navabi; Fabrizio Lombardi (Asian Test Symposium, 2003)

Using Verilog VPI for Mixed Level Serial Fault Simulation in a Test Generation Environment. - Pedram A. Riahi; Zainalabedin Navabi; Fabrizio Lombardi (Embedded Systems and Applications, 2003)

Reducing Test Power, Time and Data Volume in SoC Testing Using Selective Trigger Scan Architecture. - Shervin Sharifi; Mohammad Hosseinabady; Pedram A. Riahi; Zainalabedin Navabi (DFT, 2003)

Utilizing Various ADL Facets for Instruction Level CPU Test. - Elham Safi; Zohreh Karimi; Maghsoud Abbaspour; Zainalabedin Navabi (MTV, 2003)

Dynamic Input Buffer Allocation (DIBA) for Fault Tolerant Ethernet Packet Switching. - Morteza Fayyazi; David R. Kaeli; Zainalabedin Navabi (PDPTA, 2003)

A Low Power BIST Architecture for FPGA Look-Up Table Testing. - Ehsan Atoofian; Zainalabedin Navabi (VLSI-SOC, 2003)

Processor Testing Using an ADL Description and Genetic Algorithms. - Elham Safi; Reihaneh Saberi; Zohreh Karimi; Zainalabedin Navabi (VLSI-SOC, 2003)

Selective Trigger Scan Architecture for Reducing Power, Time and Data Volume in SoC Testing. - Shervin Sharifi; Mohammad Hosseinabady; Zainalabedin Navabi (VLSI-SOC, 2003)

Property Checking based on Hierarchical Integer Equations. - Bijan Alizadeh; Zainalabedin Navabi (ACSD, 2004)

Test Instruction Set (TIS) for High Level Self-Testing of CPU Cores. - Saeed Shamshiri; Hadi Esmaeilzadeh; Zainalabedin Navabi (Asian Test Symposium, 2004)

Instruction level test methodology for CPU core software-based self-testing. - Saeed Shamshiri; Hadi Esmaeilzadeh; Zainalabedin Navabi (HLDVT, 2004)

Using Integer Equations to Check PSL Properties in RT Level Design. - Bijan Alizadeh; Zainalabedin Navabi (IWSOC, 2004)

Using RT Level Component Descriptions for Single Stuck-at Hierarchical Fault Simulation. - Zainalabedin Navabi; Shahrzad Mirkhani; Meisam Lavasani; Fabrizio Lombardi (J. Electron. Test., 2004)

A Low-Cost At-Speed BIST Architecture for Embedded Processor and SRAM Cores. - Mohammad H. Tehranipour; Seid Mehdi Fakhraie; Zainalabedin Navabi; M. R. Movahedin (J. Electron. Test., 2004)

Using data compression in automatic test equipment for system-on-chip testing. - Farzin Karimi; Zainalabedin Navabi; Waleed Meleis; Fabrizio Lombardi (IEEE Trans. Instrum. Meas., 2004)

Digital design and implementation with field programmable devices. - Zainalabedin Navabi (Kluwer, 2005)

TED+: a data structure for microprocessor verification. - Pejman Lotfi-Kamran; Mohammad Hosseinabady; Hamid Shojaei; Mehran Massoumi; Zainalabedin Navabi (ASP-DAC, 2005)

ISC: Reconfigurable Scan-Cell Architecture for Low Power Testing. - Hadi Esmaeilzadeh; Saeed Shamshiri; Pooya Saeedi; Zainalabedin Navabi (Asian Test Symposium, 2005)

Enhancing Fault Simulation Performance by Dynamic Fault Clustering. - Shahrzad Mirkhani; Zainalabedin Navabi (Asian Test Symposium, 2005)

Simultaneous Reduction of Dynamic and Static Power in Scan Structures. - Shervin Sharifi; Javid Jaffari; Mohammad Hosseinabady; Ali Afzali-Kusha; Zainalabedin Navabi (DATE, 2005)

Simulating Faults of Combinational IP Core-based SOCs in a PLI Environment. - Pedram A. Riahi; Zainalabedin Navabi; Fabrizio Lombardi (DFT, 2005)

Combination of Assertion and HSAT Methods For Automated Test Vectors Generation. - Mostafa Naderi; Zainalabedin Navabi (FDL, 2005)

A low-power scan-path architecture. - Mohammad Alisafaee; Safar Hatami; Ehsan Atoofian; Zainalabedin Navabi; Ali Afzali-Kusha (ISCAS (5), 2005)

Binary Taylor diagrams: an efficient implementation of Taylor expansion diagrams. - Arash Hooshmand; Saeed Shamshiri; Mohammad Alisafaee; Bijan Alizadeh; Pejman Lotfi-Kamran; Mostafa Naderi; Zainalabedin Navabi (ISCAS (1), 2005)

A Flow Graph Technique for DFT Controller Modification. - Mohammad Hosseinabady; Pejman Lotfi-Kamran; Pedram A. Riahi; Fabrizio Lombardi; Zainalabedin Navabi (SoCC, 2005)

An Effective VHDL-AMS Simulation Algorithm with Event Partitioning. - Hamid Reza Ghasemi; Zainalabedin Navabi (VLSI Design, 2005)

Instruction-level test methodology for CPU core self-testing. - Saeed Shamshiri; Hadi Esmaeilzadeh; Zainalabedin Navabi (ACM Trans. Design Autom. Electr. Syst., 2005)

NoC Hot Spot minimization Using AntNet Dynamic Routing Algorithm. - Masoud Daneshtalab; Ashkan Sobhani; Ali Afzali-Kusha; Omid Fatemi; Zainalabedin Navabi (ASAP, 2006)

An Optimum ORA BIST for Multiple Fault FPGA Look-Up Table Testing. - Armin Alaghi; Mahnaz Sadoughi Yarandi; Zainalabedin Navabi (ATS, 2006)

ESTA: An Efficient Method for Reliability Enhancement of RT-Level Designs. - Naghmeh Karimi; Shahrzad Mirkhani; Zainalabedin Navabi (ATS, 2006)

A concurrent testing method for NoC switches. - Mohammad Hosseinabady; Abbas Banaiyan; Mahdi Nazm Bojnordi; Zainalabedin Navabi (DATE, 2006)

DCim++: a C++ library for object oriented hardware design and distributed simulation. - Hadi Esmaeilzadeh; A. Moghimi; Eiman Ebrahimi; Caro Lucas; Zainalabedin Navabi; A. M. Fakhraie (ISCAS, 2006)

Low-power and low-latency cluster topology for local traffic NoCs. - Mohsen Saneei; Ali Afzali-Kusha; Zainalabedin Navabi (ISCAS, 2006)

Serial Bus Encoding for Low Power Application. - Mohsen Saneei; Ali Afzali-Kusha; Zainalabedin Navabi (SoC, 2006)

A New Protocol Stack Model for Network on Chip. - Masood Deh-Yadegari; Mohsen Nickray; Ali Afzali-Kusha; Zainalabedin Navabi (ISVLSI, 2006)

An Optimized BIST Architecture for FPGA Look-Up Table Testing. - Mahnaz Sadoughi Yarandi; Armin Alaghi; Zainalabedin Navabi (ISVLSI, 2006)

Ant colony based routing architecture for minimizing hot spots in NOCs. - Masoud Daneshtalab; Ali Afzali-Kusha; Ashkan Sobhani; Zainalabedin Navabi; Mohammad D. Mottaghi; Omid Fatemi (SBCCI, 2006)

ByZFAD: a low switching activity architecture for shift-and-add multipliers. - Mohammad D. Mottaghi; Ali Afzali-Kusha; Zainalabedin Navabi (SBCCI, 2006)

A Test Approach for Look-Up Table Based FPGAs. - Ehsan Atoofian; Zainalabedin Navabi (J. Comput. Sci. Technol., 2006)

Scan-Based Structure with Reduced Static and Dynamic Power Consumption. - Shervin Sharifi; Javid Jaffari; Mohammad Hosseinabady; Ali Afzali-Kusha; Zainalabedin Navabi (J. Low Power Electron., 2006)

Optimized Assignment Coverage Computation in Formal Verification of Digital Systems. - Majid Nabi; Hamid Shojaei; Siamak Mohammadi; Zainalabedin Navabi (ATS, 2007)

An HDL-Based Platform for High Level NoC Switch Testing. - Mahshid Sedghi; Armin Alaghi; Elnaz Koopahi; Zainalabedin Navabi (ATS, 2007)

Using the inter- and intra-switch regularity in NoC switch testing. - Mohammad Hosseinabady; Atefe Dalirsani; Zainalabedin Navabi (DATE, 2007)

A HW/SW Architecture to Reduce the Effects of Soft-Errors in Real-Time Operating System Services. - Mohammad Hossein Neishaburi; Mohammad Reza Kakoee; Masoud Daneshtalab; Saeed Safari; Zainalabedin Navabi (DDECS, 2007)

Online NoC Switch Fault Detection and Diagnosis Using a High Level Fault Mode. - Armin Alaghi; Naghmeh Karimi; Mahshid Sedghi; Zainalabedin Navabi (DFT, 2007)

On-Chip Verification of NoCs Using Assertion Processors. - Mohammad Reza Kakoee; Mohammad Hossein Neishaburi; Masoud Daneshtalab; Saeed Safari; Zainalabedin Navabi (DSD, 2007)

APDL: A Processor Description Language For Design Space Exploration of Embedded Processors. - Nima Honarmand; Hasan Sohofi; Maghsoud Abbaspour; Zainalabedin Navabi (FDL, 2007)

A Configurable Transaction Level Model of a Generic Interconnection Part of Embedded Systems Used in an ESL Design Library. - Parisa Razaghi; Shahrzad Mirkhani; Zainalabedin Navabi (FDL, 2007)

RT level reliability enhancement by constructing dynamic TMRS. - Naghmeh Karimi; Shahrzad Mirkhani; Zainalabedin Navabi; Fabrizio Lombardi (ACM Great Lakes Symposium on VLSI, 2007)

An Analytical Model for Reliability Evaluation of NoC Architectures. - Atefe Dalirsani; Mohammad Hosseinabady; Zainalabedin Navabi (IOLTS, 2007)

Analysis of System-Failure Rate Caused by Soft-Errors using a UML-Based Systematic Methodology in an SoC. - Mohammad Hosseinabady; Mohammad Hossein Neishaburi; Zainalabedin Navabi; Alfredo Benso; Stefano Di Carlo; Paolo Prinetto; Giorgio Di Natale (IOLTS, 2007)

A New Approach for Design and Verification of Transaction Level Models. - Mohammad Reza Kakoee; Hamid Shojaei; Hassan Ghasemzadeh 001; Marjan Sirjani; Zainalabedin Navabi (ISCAS, 2007)

Programmable Routing Tables for Degradable Torus-Based Networks on Chips. - Ali Shahabi; Nima Honarmand; Zainalabedin Navabi (ISCAS, 2007)

High Level Synthesis of Degradable ASICs Using Virtual Binding. - Nima Honarmand; Ali Shahabi; Hasan Sohofi; Maghsoud Abbaspour; Zainalabedin Navabi (VTS, 2007)

A UML Based System Level Failure Rate Assessment Technique for SoC Designs. - Mohammad Hosseinabady; Mohammad Hossein Neishaburi; Pejman Lotfi-Kamran; Zainalabedin Navabi (VTS, 2007)

Degradable mesh-based on-chip networks using programmable routing tables. - Ali Shahabi; Nima Honarmand; Hasan Sohofi; Zainalabedin Navabi (IEICE Electron. Express, 2007)

Low overhead DFT using CDFG by modifying controller. - Mohammad Hosseinabady; Pejman Lotfi-Kamran; Fabrizio Lombardi; Zainalabedin Navabi (IET Comput. Digit. Tech., 2007)

Low test application time resource binding for behavioral synthesis. - Mohammad Hosseinabady; Pejman Lotfi-Kamran; Zainalabedin Navabi (ACM Trans. Design Autom. Electr. Syst., 2007)

BARP-A Dynamic Routing Protocol for Balanced Distribution of Traffic in NoCs. - Pejman Lotfi-Kamran; Masoud Daneshtalab; Caro Lucas; Zainalabedin Navabi (DATE, 2008)

Reliable NoC architecture utilizing a robust rerouting algorithm. - Armin Alaghi; Mahshid Sedghi; Naghmeh Karimi; Mahmood Fathy; Zainalabedin Navabi (EWDTS, 2008)

Utilizing HDL simulation engines for accelerating design and test processes. - Najmeh Farajipour; S. Behdad Hosseini; Zainalabedin Navabi (EWDTS, 2008)

An advanced method for synthesizing TLM2-based interfaces. - Nadereh Hatami; Zainalabedin Navabi (EWDTS, 2008)

System level hardware design and simulation with SystemAda. - Negin Mahani; Parnian Mokri; Zainalabedin Navabi (EWDTS, 2008)

Automating Hardware/Software partitioning using dependency Graph. - Somayeh Malekshahi; Mahshid Sedghi; Zainalabedin Navabi (EWDTS, 2008)

An IEEE 1500 compatible wrapper architecture for testing cores at transaction level. - Fatemeh Refan; Paolo Prinetto; Zainalabedin Navabi (EWDTS, 2008)

Functional testing approaches for "BIFST-able" tlm_fifo. - Homa Alemzadeh; Zainalabedin Navabi; Stefano Di Carlo; Alberto Scionti; Paolo Prinetto (HLDVT, 2008)

A Novel GA-Based High-Level Synthesis Technique to Enhance RT-Level Concurrent Testing. - Naghmeh Karimi; Soheil Aminzadeh; Saeed Safari; Zainalabedin Navabi (IOLTS, 2008)

Reliability in Application Specific Mesh-Based NoC Architectures. - Fatemeh Refan; Homa Alemzadeh; Saeed Safari; Paolo Prinetto; Zainalabedin Navabi (IOLTS, 2008)

NoC Reconfiguration for Utilizing the Largest Fault-free Connected Sub-structure. - Armin Alaghi; Mahshid Sedghi; Naghmeh Karimi; Zainalabedin Navabi (ITC, 2008)

"Plug & Test" at System Level via Testable TLM Primitives. - Homa Alemzadeh; Stefano Di Carlo; Fatemeh Refan; Paolo Prinetto; Zainalabedin Navabi (ITC, 2008)

Enhanced TED: A New Data Structure for RTL Verification. - Pejman Lotfi-Kamran; Mehran Massoumi; Mohammad Mirzaei; Zainalabedin Navabi (VLSI Design, 2008)

Stall Power Reduction in Pipelined Architecture Processors. - Pejman Lotfi-Kamran; Amir-Mohammad Rahmani; Ali-Asghar Salehpour; Ali Afzali-Kusha; Zainalabedin Navabi (VLSI Design, 2008)

An NoC Test Strategy Based on Flooding with Power, Test Time and Coverage Considerations. - Mahshid Sedghi; Elnaz Koopahi; Armin Alaghi; Mahmood Fathy; Zainalabedin Navabi (VLSI Design, 2008)

Online Network-on-Chip Switch Fault Detection and Diagnosis Using Functional Switch Faults. - Naghmeh Karimi; Armin Alaghi; Mahshid Sedghi; Zainalabedin Navabi (J. Univers. Comput. Sci., 2008)

A Selective Trigger Scan Architecture for VLSI Testing. - Mohammad Hosseinabady; Shervin Sharifi; Fabrizio Lombardi; Zainalabedin Navabi (IEEE Trans. Computers, 2008)

Optimizing Parametric BIST Using Bio-inspired Computing Algorithms. - Nastaran Nemati; Amirhossein Simjour; Amirali Ghofrani; Zainalabedin Navabi (DFT, 2009)

Emotion on FPGA: Model driven approach. - Mohammad Reza Jamali; Arash Arami; Masood Deh-Yadegari; Caro Lucas; Zainalabedin Navabi (Expert Syst. Appl., 2009)

Sign Bit Reduction Encoding For Low Power Applications. - Mohsen Saneei; Ali Afzali-Kusha; Zainalabedin Navabi (J. Signal Process. Syst., 2009)

Test Pattern Selection and Compaction for Sequential Circuits in an HDL Environment. - M. H. Haghbayan; Sara Karamati; Fatemeh Javaheri; Zainalabedin Navabi (Asian Test Symposium, 2010)

A reconfigurable online BIST for combinational hardware using digital neural networks. - S. Behdad Hosseini; Ali Shahabi; Hasan Sohofi; Zainalabedin Navabi (ETS, 2010)

Code optimization for enhancing SystemC simulation time. - Homa Alemzadeh; Soheil Aminzadeh; Reihaneh Saberi; Zainalabedin Navabi (EWDTS, 2010)

Facilitating testability of TLM FIFO: SystemC implementations. - Homa Alemzadeh; Marco Cimei; Paolo Prinetto; Zainalabedin Navabi (EWDTS, 2010)

A TLM2.0 assertion library with centralized monitoring approach. - Amirali Ghofrani; Sheis Abolma'ali; Zahra Najafi Haghi; Zainalabedin Navabi (EWDTS, 2010)

Assertion based verification in TLM. - Amirali Ghofrani; Fatemeh Javaheri; Zainalabedin Navabi (EWDTS, 2010)

Architecture design and technical methodology for bus testing. - M. H. Haghbayan; Zainalabedin Navabi (EWDTS, 2010)

Generating test patterns for sequential circuits using random patterns by PLI functions. - Mohammad Hashem Haghbayan; Alireza Yazdanpanah; Sara Karamati; Ramyar Saeedi; Zainalabedin Navabi (EWDTS, 2010)

ESL design methodology for architecture exploration. - Fatemeh Javaheri; Zainalabedin Navabi (EWDTS, 2010)

Merit based directed random test generation (MDRTG) scheme for combinational circuits. - Arezoo Kamran; Mohammad Saeed Jahangiry; Zainalabedin Navabi (EWDTS, 2010)

Virtual tester development using HDL/PLI. - Arezoo Kamran; Nastaran Nemati; Somayeh Sadeghi Kohan; Zainalabedin Navabi (EWDTS, 2010)

A mixed HDL/PLI test package. - Nastaran Nemati; Majid Namaki-Shoushtari; Zainalabedin Navabi (EWDTS, 2010)

Low cost error tolerant motion estimation for H.264/AVC standard. - Mohammad Hossein Sargolzaei; Mehdi Semsarzadeh; Mahmoud Reza Hashemi; Zainalabedin Navabi (EWDTS, 2010)

Near optimal machine learning based random test generation. - Niki Shakeri; Nastaran Nemati; Majid Nili Ahmadabadi; Zainalabedin Navabi (EWDTS, 2010)

A partitioning approach to improve reconfigurable neuron-inspired online BIST. - Ali Shahabi; S. Behdad Hosseini; Hasan Sohofi; Zainalabedin Navabi (IOLTS, 2010)

Automatic selection of efficient observability points in combinational gate level circuits using particle swarm optimization. - Amirali Ghofrani; Fatemeh Javaheri; Saeed Safari; Zainalabedin Navabi (SoC, 2010)

Using context based methods for test data compression. - Sara Karamati; Zainalabedin Navabi (ITC, 2010)

EDXY - A low cost congestion-aware routing algorithm for network-on-chips. - Pejman Lotfi-Kamran; Amir-Mohammad Rahmani; Masoud Daneshtalab; Ali Afzali-Kusha; Zainalabedin Navabi (J. Syst. Archit., 2010)

Real-time embedded emotional controller. - Mohammad Reza Jamali; Masood Deh-Yadegari; Arash Arami; Caro Lucas; Zainalabedin Navabi (Neural Comput. Appl., 2010)

Mapping Transaction Level Faults to Stuck-At Faults in Communication Hardware. - Fatemeh Javaheri; Majid Namaki-Shoushtari; Parastoo Kamranfar; Zainalabedin Navabi (Asian Test Symposium, 2011)

Online Test Macro Scheduling and Assignment in MPSoC Design. - Behnam Khodabandeloo; Seyyed Alireza Hoseini; Sajjad Taheri; Mohammad Hashem Haghbayan; Mahmood Reza Babaei; Zainalabedin Navabi (Asian Test Symposium, 2011)

Adaptation of Standard RT Level BIST Architectures for System Level Communication Testing. - Nastaran Nemati; Zainalabedin Navabi (Asian Test Symposium, 2011)

Configurable architecture for memory BIST. - Atieh Lotfi; Parisa Kabiri; Zainalabedin Navabi (EWDTS, 2011)

A Probabilistic and Constraint Based Approach for Low Power Test Generation. - Hossein Sabaghian Bidgoli; Majid Namaki-Shoushtari; Zainalabedin Navabi (Asian Test Symposium, 2012)

Power constraint testing for multi-clock domain SoCs using concurrent hybrid BIST. - M. H. Haghbayan; Saeed Safari; Zainalabedin Navabi (DDECS, 2012)

Effective RT-level software-based self-testing of embedded processor cores. - Parisa Kabiri; Zainalabedin Navabi (DDECS, 2012)

Soft Error Analysis on Communication Channels in On-Chip Communication Networks. - Mohammadreza Najafi; Saeed Safari; Zainalabedin Navabi (DSD, 2012)

A novel graceful degradable routing algorithm for 3D on-chip networks. - Reza Nakhjavani; Ali Shahabi; Saeed Safari; Zainalabedin Navabi (INA-OCMC@HiPEAC, 2012)

BS 1149.1 extensions for an online interconnect fault detection and recovery. - Somayeh Sadeghi Kohan; Majid Namaki-Shoushtari; Fatemeh Javaheri; Zainalabedin Navabi (ITC, 2012)

Polynomial datapath synthesis and optimization based on vanishing polynomial over Z2m and algebraic techniques. - Samaneh Ghandali; Bijan Alizadeh; Zainalabedin Navabi; Masahiro Fujita (MEMOCODE, 2012)

A probabilistic approach for counterexample generation to aid design debugging. - Payman Behnam; Hossein Sabaghian Bidgoli; Bijan Alizadeh; Kamyar Mohajerani; Zainalabedin Navabi (EWDTS, 2013)

Extracting complete set of equations to analyze VHDL-AMS descriptions. - Arezoo Kamran; Vahid Janfaza; Zainalabedin Navabi (EWDTS, 2013)

A new structure for interconnect offline testing. - Somayeh Sadeghi Kohan; Shahrzad Keshavarz; Farzaneh Zokaee; Farimah Farahmandi; Zainalabedin Navabi (EWDTS, 2013)

Online periodic test mechanism for homogeneous many-core processors. - Arezoo Kamran; Zainalabedin Navabi (VLSI-SoC, 2013)

Embedded tutorials: Embedded tutorial 1: Cell-aware test-from gates to transistors. - Janusz Rajski; Miodrag Potkonjak; Adit D. Singh; Abhijit Chatterjee; Zain Navabi; Matthew R. Guthaus; Sezer Gören 001 (VLSI-SoC, 2013)

A New Approach for Automatic Test Pattern Generation in Register Transfer Level Circuits. - Mohammad Mirzaei; Mahmoud Tabandeh; Bijan Alizadeh; Zainalabedin Navabi (IEEE Des. Test, 2013)

A heuristic path selection method for small delay defects test. - Paniz Foroutan; Mehdi Kamal; Zainalabedin Navabi (DFT, 2014)

Preemptive multi-bit IJTAG testing with reconfigurable infrastructure. - Shahrzad Keshavarz; Amirreza Nekooei; Zainalabedin Navabi (DFT, 2014)

Automatic correction of certain design errors using mutation technique. - Payman Behnam; Bijan Alizadeh; Zainalabedin Navabi (ETS, 2014)

Homogeneous many-core processor system test distribution and execution mechanism. - Arezoo Kamran; Zainalabedin Navabi (ETS, 2014)

Improving polynomial datapath debugging with HEDs. - Somayeh Sadeghi Kohan; Payman Behnam; Bijan Alizadeh; Masahiro Fujita; Zainalabedin Navabi (ETS, 2014)

An off-line MDSI interconnect BIST incorporated in BS 1149.1. - Marzieh Mohammadi; Somayeh Sadeghi Kohan; Nasser Masoumi; Zainalabedin Navabi (ETS, 2014)

RTL datapath optimization using system-level transformations. - Samaneh Ghandali; Bijan Alizadeh; Masahiro Fujita; Zainalabedin Navabi (ISQED, 2014)

Assertion-based verification for system-level designs. - Hasan Sohofi; Zainalabedin Navabi (ISQED, 2014)

Effective Combination of Algebraic Techniques and Decision Diagrams to Formally Verify Large Arithmetic Circuits. - Farimah Farahmandi; Bijan Alizadeh; Zainalabedin Navabi (ISVLSI, 2014)

Back-annotation of gate-level power properties into system level descriptions. - Najmeh Farajipour Ghohroud; Zainalabedin Navabi (NEWCAS, 2014)

Configurable Systolic Matrix Multiplication. - Parastoo Kamranfar; Ali Shahabi; Ghazaleh Vazhbakht; Zainalabedin Navabi (VLSID, 2014)

High-level design space exploration of locally linear neuro-fuzzy models for embedded systems. - Mohammadreza Baharani; Hamid Noori; Mohammad Aliasgari; Zain Navabi (Fuzzy Sets Syst., 2014)

Power-aware online testing of manycore systems in the dark silicon era. - Mohammad Hashem Haghbayan; Amir-Mohammad Rahmani; Mohammad Fattah; Pasi Liljeberg; Juha Plosila; Zainalabedin Navabi; Hannu Tenhunen (DATE, 2015)

Application-specific power-aware mapping for reconfigurable NoC architectures. - Mehran Goli; Amin Ghasemazar; Zainalabedin Navabi (DTIS, 2015)

Utilizing NOPs for online deterministic testing of simple processing cores. - Rasoul Jafari; Elham Zahraei Salehi; Zain Navabi (DTIS, 2015)

Online self adjusting progressive age monitoring of timing variations. - Somayeh Sadeghi Kohan; Mehdi Kamal; John McNeil; Paolo Prinetto; Zain Navabi (DTIS, 2015)

HDLs evolve as they affect design methodology for a higher abstraction and a better integration. - Zainalabedin Navabi (DTIS, 2015)

Multi-valued logic test access mechanism for test time and power reduction. - Amirreza Nekooei; Zainalabedin Navabi (DTIS, 2015)

Aging in digital circuits and age monitoring: Object-oriented modeling and evaluation. - Somayeh Sadeghi Kohan; Arezoo Kamran; Farnaz Forooghifar; Zainalabedin Navabi (DTIS, 2015)

Low power scheduling in high-level synthesis using dual-Vth library. - Samaneh Ghandali; Bijan Alizadeh; Zainalabedin Navabi (ISQED, 2015)

Accelerated On-chip Communication Test Methodology Using a Novel High-Level Fault Model. - Elmira Karimi; Mohammad Hashem Haghbayan; Amir-Mohammad Rahmani; Mahmoud Tabandeh; Pasi Liljeberg; Zainalabedin Navabi (MCSoC, 2015)

Signature oriented model pruning to facilitate multi-threaded processors debugging. - Fatemeh Refan; Bijan Alizadeh; Zainalabedin Navabi (VTS, 2015)

System-level assertions: approach for electronic system-level verification. - Hasan Sohofi; Zainalabedin Navabi (IET Comput. Digit. Tech., 2015)

A near-threshold 7T SRAM cell with high write and read margins and low write time for sub-20 nm FinFET technologies. - Mohammad Ansari; Hassan Afzali-Kusha; Behzad Ebrahimi; Zainalabedin Navabi; Ali Afzali-Kusha; Massoud Pedram (Integr., 2015)

Automatic High-Level Data-Flow Synthesis and Optimization of Polynomial Datapaths Using Functional Decomposition. - Samaneh Ghandali; Bijan Alizadeh; Masahiro Fujita; Zainalabedin Navabi (IEEE Trans. Computers, 2015)

Path selection and sensor insertion flow for age monitoring in FPGAs. - Mohammad Ebrahimi; Zana Ghaderi; Eli Bozorgzadeh; Zain Navabi (DATE, 2016)

ESL design with RTL-verified predesigned abstract communication channels. - Hamed Najafi Haghi; Mikhail M. Chupilko; Alexander S. Kamkin; Zainalabedin Navabi (EWDTS, 2016)

Universal mitigation of NBTI-induced aging by design randomization. - Maksim Jenihhin; Alexander Kamkin; Zainalabedin Navabi; Somayeh Sadeghi Kohan (EWDTS, 2016)

An improved scheme for pre-computed patterns in core-based SoC architecture. - Elaheh Sadredini; Reza Rahimi; Paniz Foroutan; Mahmood Fathy; Zainalabedin Navabi (EWDTS, 2016)

Prolonging Lifetime of Non-volatile Last Level Caches with Cluster Mapping. - Morteza Soltani; Mohammad Ebrahimi; Zainalabedin Navabi (ACM Great Lakes Symposium on VLSI, 2016)

Optimistic clock adjustment for preventing Better-than-worst-case violations. - Seyedeh Hanieh Hashemi; Reza Namazian; Zainalabedin Navabi (VLSI-SoC, 2016)

Stochastic testing of processing cores in a many-core architecture. - Arezoo Kamran; Zainalabedin Navabi (Integr., 2016)

Self-Healing Many-Core Architecture: Analysis and Evaluation. - Arezoo Kamran; Zainalabedin Navabi (VLSI Design, 2016)

TruncApp: A truncation-based approximate divider for energy efficient DSP applications. - Shaghayegh Vahdat; Mehdi Kamal; Ali Afzali-Kusha; Massoud Pedram; Zainalabedin Navabi (DATE, 2017)

Online Profiling for cluster-specific variable rate refreshing in high-density DRAM systems. - Rasool Sharifi; Zainalabedin Navabi (ETS, 2017)

A novel SAT-based ATPG approach for transition delay faults. - Farzaneh Zokaee; Hossein Sabaghian Bidgoli; Vahid Janfaza; Payman Behnam; Zainalabedin Navabi (HLDVT, 2017)

Reducing Search Space for Fault Diagnosis: A Probability-Based Scoring Approach. - Hossein Sabaghian Bidgoli; Payman Behnam; Bijan Alizadeh; Zainalabedin Navabi (ISVLSI, 2017)

BILBO-friendly Hybrid BIST Architecture with Asymmetric Polynomial Reseeding. - Elaheh Sadredini; Mohammadreza Najafi; Mahmood Fathy; Zainalabedin Navabi (CoRR, 2017)

Test Generation and Scheduling for a Hybrid BIST Considering Test Time and Power Constraint. - Elaheh Sadredini; Mohammad Hashem Haghbayan; Mahmood Fathy; Zainalabedin Navabi (CoRR, 2017)

SENSIBle: A Highly Scalable SENsor DeSIgn for Path-Based Age Monitoring in FPGAs. - Zana Ghaderi; Mohammad Ebrahimi; Zainalabedin Navabi; Eli Bozorgzadeh; Nader Bagherzadeh (IEEE Trans. Computers, 2017)

Bridging Presilicon and Postsilicon Debugging by Instruction-Based Trace Signal Selection in Modern Processors. - Fatemeh Refan; Bijan Alizadeh; Zainalabedin Navabi (IEEE Trans. Very Large Scale Integr. Syst., 2017)

Performance and Energy Enhancement through an Online Single/Multi Level Mode Switching Cache Architecture. - Ramin Rezaeizadeh Rookerd; Somayeh Sadeghi Kohan; Zainalabedin Navabi (ACM Great Lakes Symposium on VLSI, 2018)

Near-Optimal Node Selection Procedure for Aging Monitor Placement. - Somayeh Sadeghi Kohan; Arash Vafaei; Zainalabedin Navabi (IOLTS, 2018)

Scalable Symbolic Simulation-Based Automatic Correction of Modern Processors. - Fatemeh Refan; Bijan Alizadeh; Zainalabedin Navabi (IEEE Trans. Very Large Scale Integr. Syst., 2018)

Automatic Correction of Dynamic Power Management Architecture in Modern Processors. - Reza Sharafinejad; Bijan Alizadeh; Zainalabedin Navabi (IEEE Trans. Very Large Scale Integr. Syst., 2018)

Test Adapted Shielding by a Multipurpose Crosstalk Avoidance Scheme. - Mahsa Akhsham; Atefesadat Seyedolhosseini; Zainalabedin Navabi (ETS, 2019)

Back-annotation of Interconnect Physical Properties for System-Level Crosstalk Modeling. - Rezgar Sadeghi; Nooshin Nosrati; Katayoon Basharkhah; Zainalabedin Navabi (ETS, 2019)

From Abstract Modeling of ADAS Applications to an Accelerator-based Hardware Realization. - Samira Ahmadi Farsani; Katayoon Basharkhah; Amin Mohaghegh; Zainalabedin Navabi (EWDTS, 2019)

SCOAP-based Directed Random Test Generation for Combinational Circuits. - Seyyede Maryam Ghasemy; Maryam Rajabalipanah; Saeideh Sarmadi; Zainalabedin Navabi (EWDTS, 2019)

Making System Level Test Possible by a Mixed-mode, Multi-level, Integrated Modeling Environment. - Nooshin Nosrati; Katayoon Basharkhah; Rezgar Sadeghi; Carna Zivkovic; Christoph Grimm 001; Zainalabedin Navabi (EWDTS, 2019)

An Accelerator-based Architecture Utilizing an Efficient Memory Link for Modern Computational Requirements. - Saba Yousefzadeh; Katayoon Basharkhah; Nooshin Nosrati; Rezgar Sadeghi; Jaan Raik; Maksim Jenihhin; Zainalabedin Navabi (EWDTS, 2019)

An ESL Environment for Modeling Electrical Interconnect Faults. - Nooshin Nosrati; Katayoon Basharkhah; Rezgar Sadeghi; Zainalabedin Navabi (ISVLSI, 2019)

DiBA: n-Dimensional Bitslice Architecture for LSTM Implementation. - Mahboobe Sadeghipour Roodsari; Mohamad Ali Saber; Zainalabedin Navabi (DDECS, 2020)

Reconfiguration of Embedded Accelerators by Microprogramming for Intensive Loop Computations. - Saba Yousefzadeh; Katayoon Basharkhah; Nooshin Nosrati; Maryam Rajabalipanah; Seyedeh Maryam Ghasemi; Zainalabedin Navabi (DDECS, 2020)

Reducing DFT hardware overhead by use of a test microprogram in a microprogrammed hardware accelerator. - Maryam Rajabalipanah; Seyedeh Maryam Ghasemi; Nooshin Nosrati; Katayoon Basharkhah; Saba Yousefzadeh; Zainalabedin Navabi (DFT, 2020)

Built-In Predictors for Dynamic Crosstalk Avoidance. - Rezgar Sadeghi; Zainalabedin Navabi (ETS, 2020)

ESL, Back-annotating Crosstalk Fault Models into High-level Communication Links. - Katayoon Basharkhah; Rezgar Sadeghi; Nooshin Nosrati; Zainalabedin Navabi (VTS, 2020)

LUT Input Reordering to Reduce Aging Impact on FPGA LUTs. - Mohammad Ebrahimi; Rezgar Sadeghi; Zainalabedin Navabi (IEEE Trans. Computers, 2020)

Selecting Representative Critical Paths for Sensor Placement Provides Early FPGA Aging Information. - Mohammad Ebrahimi; Zainalabedin Navabi (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020)

Self-Adjusting Monitor for Measuring Aging Rate and Advancement. - Somayeh Sadeghi Kohan; Mehdi Kamal; Zainalabedin Navabi (IEEE Trans. Emerg. Top. Comput., 2020)

Testing a RISCV-Like Architecture With an HDL-Based Virtual Tester. - Nooshin Nosrati; Katayoon Basharkhah; Hanieh Totonchi Asl; Zahra Mahdavi; Zainalabedin Navabi (DTIS, 2021)

Online Testing of a Row-Stationary Convolution Accelerator. - Mohammad Rasoul Roshanshah; Katayoon Basharkhah; Zainalabedin Navabi (ETS, 2021)

AFTAB: A RISC-V Implementation with Configurable Gateways for Security. - Maryam Rajabalipanah; Mahboobe Sadeghipour Roodsari; Zahra Jahanpeima; Gianluca Roascio; Paolo Prinetto; Zainalabedin Navabi (EWDTS, 2021)

Integrating an Interconnect BIST with Crosstalk Avoidance Hardware. - Mahsa Akhsham; Zainalabedin Navabi (IOLTS, 2021)

n-DiCE-LSTM: An n-Dimensional Configurable and Efficient Architecture for LSTM Accelerator. - Mahboobe Sadeghipour Roodsari; Hanieh Totonchi Asl; Zainalabedin Navabi (ISVLSI, 2021)

Concurrent Error Detection for LSTM Accelerators. - Nooshin Nosrati; Seyedeh Maryam Ghasemi; Mahboobe Sadeghipour Roodsari; Zainalabedin Navabi (ETS, 2022)

MLC: A Machine Learning Based Checker For Soft Error Detection In Embedded Processors. - Nooshin Nosrati; Maksim Jenihhin; Zainalabedin Navabi (IOLTS, 2022)

A Secure Canary-Based Hardware Approach Against ROP. - Mahboobe Sadeghipour Roodsari; Ebrahim Nouri; Fatemeh Sheikhshoaei; Paolo Prinetto; Zainalabedin Navabi (ITASEC, 2022)

Testable Array Multipliers for a Better Utilization of C-Testability and Bijectivity. - Fatemeh Sheikh Shoaei; Alireza Nahvy; Zainalabedin Navabi (CoRR, 2022)

A Low-Cost Combinational Approximate Multiplier. - Zahra Hojati; Zainalabedin Navabi (DDECS, 2023)

A Low-cost Residue-based Scheme for Error-resiliency of RNN Accelerators. - Nooshin Nosrati; Zainalabedin Navabi (DDECS, 2023)

LiFi-CFI: Light-weight Fine-grained Hardware CFI Protection for RISC-V. - Mahboobe Sadeghipour Roodsari; Fatemeh Sheikhshoaei; Nicolò Maunero; Paolo Prinetto; Zain Navabi (DTTIS, 2023)

Learning Electrical Behavior of Core Interconnects for System-Level Crosstalk Prediction. - Katayoon Basharkhah; Raheleh Sadat Mirhashemi; Nooshin Nosrati; Mohammad-Javad Zare; Zainalabedin Navabi (ETS, 2023)

Multi-Level Fault Injection Methodology Using UVM-SystemC. - Ebrahim Nouri; Nooshin Nosrati; Hanieh Totonchi Asl; Mozhgan Rezaie Manavand; Zainalabedin Navabi (EWDTS, 2023)

HIRMA: High-Performance Implementation for RISC-V Microcontroller Applications. - Negin Safari; Amirmahdi Joudi; Maryam Rajabalipanah; Zahra Jahanpeima; Hasan Sadeghzadeh; Zainalabedin Navabi (EWDTS, 2023)

Real-Time Automotive Accident Detection Using Unsupervised Machine Learning. - Reza Baharvand; Mahsa Jamshidi; Mozhgan Rezaie Manavand; Rezgar Sadeghi; Zainalabedin Navabi (EWDTS, 2024)

Configurable DRAM Access for Neural Network Accelerators: A SystemC Virtual Platform Approach. - Tina Hashemi; Rezgar Sadeghi; Maryam Rajabalipanah; Zahra Hojati; Zainalabedin Navabi (EWDTS, 2024)

Sharing AES Engine for RISC-V Custom Instructions Performing Encryption and Decryption. - Zahra Hojati; Zahra Jahanpeima; Maryam Rajabalipanah; Hossein Ta'ati; Atefe Rabiei; Zainalabedin Navabi (EWDTS, 2024)

A Hierarchy of Machine Learning Processing Elements with Joint Micro Programmable Computation and Indexing. - Sepideh Kheirollahi; Sinatra Babele Khanshan; Zainalabedin Navabi (EWDTS, 2024)

AZMA: A Zynq-Based Monitoring and Fault Injection Framework for Processor Assessment. - Zahra Mahdavi; Rezgar Sadeghi; Ali Shayanpour; Amirhosein Yazdanpanah; Zainalabedin Navabi (EWDTS, 2024)

LBIST Configuration and Golden Signature Extraction of Black Box IP Cores. - Fatemeh Mohammadzadeh; Zeynab Sanati Najar; Zainalabedin Navabi (EWDTS, 2024)

Event-Based Power Analysis Integrated with Timing Characterization and Logic Simulation. - Katayoon Basharkhah; Zainalabedin Navabi (ISVLSI, 2024)

Analysis and Enhancement of Resilience for LSTM Accelerators Using Residue-Based CEDs. - Nooshin Nosrati; Zainalabedin Navabi (IEEE Access, 2024)

Pico-Programmable Neurons to Reduce Computations for Deep Neural Network Accelerators. - Alireza Nahvy; Zainalabedin Navabi (IEEE Trans. Very Large Scale Integr. Syst., 2024)

Domain-Specific Design Abstraction with Emphasis on Neural Networks. - Maryam Rajabalipanah; Zahra Hojati; Zahra Jahanpeima; Zainalabedin Navabi (DDECS, 2025)

European Test Symposium Teams: an Anniversary Snapshot. - Maksim Jenihhin; Jaan Raik; Artur Jutman; Natalia Cherezova; Raimund Ubar; Liviu Miclea; Szilárd Enyedi; I. Stefan; Ovidiu Stan; Cosmina Corches; Z. Peng; Petru Eles; et al. (ETS, 2025)

An Integrated Framework for Aging Analysis Based on an Age-Aware Cell Library. - Amirmahdi Joudi; Negin Safari; Fatemeh Mohammadzadeh; Katayoon Basharkhah; Fatemeh Sheikhshoaei; Zainalabedin Navabi (ETS, 2025)

SCiMA: A Systolic CiM-Based Accelerator With a New Weight Mapping for CNNs - A Virtual Framework Approach. - Rezgar Sadeghi; Zainalabedin Navabi (IEEE Access, 2025)