Test-Per-Clock Logic BIST with Semi-Deterministic Test Patterns and Zero-Aliasing Compactor. - Ondrej Novák; Zdenek Plíva; Jiri Nosek; Andrzej Hlawiczka; Tomasz Garbolino; Krzysztof Gucwa (J. Electron. Test., 2004)

COMPAS - Compressed Test Pattern Sequencer for Scan Based Circuits. - Ondrej Novák; Jirí Zahrádka; Zdenek Plíva (EDCC, 2005)

Self Testing SoC with Reduced Memory Requirements and Minimized Hardware Overhead. - Ondrej Novák; Zdenek Plíva; Jiri Jenícek; Zbynek Mader; Michal Jarkovský (DFT, 2006)

On measurement of impact of the metallization and FPGA design to the changes of slice parameters and generation of delay faults. - Petr Pfeifer; Zdenek Plíva (FPL, 2012)

On performance estimation of a scalable VLIW soft-core in XILINX FPGAs. - Petr Pfeifer; Zdenek Plíva; Mario Schölzel; Tobias Koal; Heinrich Theodor Vierhaus (DDECS, 2013)

On measurement of parameters of programmable microelectronic nanostructures under accelerating extreme conditions (Xilinx 28nm XC7Z020 Zynq FPGA). - Petr Pfeifer; Zdenek Plíva (FPL, 2013)

On reliability enhancement using adaptive core voltage scaling and variations on nanoscale FPGAs. - Petr Pfeifer; Zdenek Plíva; Pieter Weckx; Ben Kaczer (LATW, 2014)

A new method for in situ measurement of parameters and degradation processes in modern nanoscale programmable devices. - Petr Pfeifer; Zdenek Plíva (Microprocess. Microsystems, 2014)

Design and optimisation of NiTi pressure gauge. - Martin Hunek; Zdenek Plíva (DDECS, 2017)

Logic testing with test-per-clock pattern loading and improved diagnostic abilities. - Ondrej Novák; Zdenek Plíva (DDECS, 2017)

Test response compaction method with improved detection and diagnostic abilities. - Ondrej Novák; Zdenek Plíva (Microelectron. Reliab., 2018)

Detection of NAT64/DNS64 by SRV Records: Detection Using Global DNS Tree in the World Beyond Plain-Text DNS. - Martin Hunek; Zdenek Plíva (CN, 2020)