On the Practical Limits of the Evolutionary Digital Filter Design at the Gate Level. - Lukás Sekanina; Zdenek Vasícek (EvoWorkshops, 2006)

Evaluation of a New Platform For Image Filter Evolution. - Zdenek Vasícek; Lukás Sekanina (AHS, 2007)

An area-efficient alternative to adaptive median filtering in FPGAs. - Zdenek Vasícek; Lukás Sekanina (FPL, 2007)

Reducing the Area on a Chip Using a Bank of Evolved Filters. - Zdenek Vasícek; Lukás Sekanina (ICES, 2007)

Gate-Level Evolutionary Development Using Cellular Automata. - Michal Bidlo; Zdenek Vasícek (AHS, 2008)

Analysis of Reconfiguration Options for a Reconfigurable Polymorphic Circuit. - Zdenek Vasícek; Ladislav Capka; Lukás Sekanina (AHS, 2008)

Novel Hardware Implementation of Adaptive Median Filters. - Zdenek Vasícek; Lukás Sekanina (DDECS, 2008)

Hardware Accelerators for Cartesian Genetic Programming. - Zdenek Vasícek; Lukás Sekanina (EuroGP, 2008)

Cellular Automata-Based Development of Combinational and Polymorphic Circuits: A Comparative Study. - Michal Bidlo; Zdenek Vasícek (ICES, 2008)

On Evolutionary Synthesis of Linear Transforms in FPGA. - Zdenek Vasícek; Martin Zádník; Lukás Sekanina; Jirí Tobola (ICES, 2008)

Comparison of the Uniform and Non-Uniform Cellular Automata-Based Approach to the Development of Combinational Circuits. - Michal Bidlo; Zdenek Vasícek (AHS, 2009)

Evolution of Impulse Bursts Noise Filters. - Zdenek Vasícek; Michal Bidlo; Lukás Sekanina; Jim Tørresen; Kyrre Glette; Marcus Furuholmen (AHS, 2009)

Investigating gate-level evolutionary development of combinational multipliers using enhanced cellular automata-based model. - Michal Bidlo; Zdenek Vasícek (IEEE Congress on Evolutionary Computation, 2009)

Development of combinational circuits using non-uniform cellular automata: initial results. - Michal Bidlo; Zdenek Vasícek (GECCO, 2009)

REPOMO32 - New reconfigurable polymorphic integrated circuit for adaptive hardware. - Lukás Sekanina; Richard Ruzicka; Zdenek Vasícek; Roman Prokop; Lukás Fujcik (WEAH, 2009)

A method for design of impulse bursts noise filters optimized for FPGA implementations. - Zdenek Vasícek; Lukás Sekanina; Michal Bidlo (DATE, 2010)

On logic synthesis of conventionally hard to synthesize circuits using genetic programming. - Petr Fiser; Jan Schmidt; Zdenek Vasícek; Lukás Sekanina (DDECS, 2010)

Sorting Network Development Using Cellular Automata. - Michal Bidlo; Zdenek Vasícek; Karel Slaný (ICES, 2010)

Evolutionary design of efficient and robust switching image filters. - Zdenek Vasícek; Michal Bidlo; Lukás Sekanina; Kyrre Glette (AHS, 2011)

Evolutionary design of robust noise-specific image filters. - Zdenek Vasícek; Michal Bidlo (IEEE Congress on Evolutionary Computation, 2011)

A global postsynthesis optimization method for combinational circuits. - Zdenek Vasícek; Lukás Sekanina (DATE, 2011)

Formal verification of candidate solutions for post-synthesis evolutionary optimization in evolvable hardware. - Zdenek Vasícek; Lukás Sekanina (Genet. Program. Evolvable Mach., 2011)

CGP Acceleration Using Field-Programmable Gate Arrays. - Lukás Sekanina; Zdenek Vasícek (Cartesian Genetic Programming, 2011)

Cellular Automaton as Sorting Network Generator Using Instruction-Based Development. - Michal Bidlo; Zdenek Vasícek (ACRI, 2012)

Evolution of cellular automata using instruction-based approach. - Michal Bidlo; Zdenek Vasícek (IEEE Congress on Evolutionary Computation, 2012)

Two-step evolution of polymorphic circuits for image multi-filtering. - Lukás Sekanina; Vojtech Salajka; Zdenek Vasícek (IEEE Congress on Evolutionary Computation, 2012)

On area minimization of complex combinational circuits using cartesian genetic programming. - Zdenek Vasícek; Lukás Sekanina (IEEE Congress on Evolutionary Computation, 2012)

A SAT-based fitness function for evolutionary optimization of polymorphic circuits. - Lukás Sekanina; Zdenek Vasícek (DATE, 2012)

Efficient Phenotype Evaluation in Cartesian Genetic Programming. - Zdenek Vasícek; Karel Slaný (EuroGP, 2012)

Acceleration Methods for Evolutionary Design of Digital Circuits. - Zdenek Vasícek (2012)

Evolution of cellular automata with conditionally matching rules. - Michal Bidlo; Zdenek Vasícek (IEEE Congress on Evolutionary Computation, 2013)

Functional-level development of image filters by means of cellular automata. - Michal Bidlo; Zdenek Vasícek (ICES, 2013)

Approximate circuit design by means of evolvable hardware. - Lukás Sekanina; Zdenek Vasícek (ICES, 2013)

Implementing A Unique Chip Id On A Reconfigurable Polymorphic Circuit. - Lukás Sekanina; Richard Ruzicka; Zdenek Vasícek; Václav Simek; Petr Hanácek (Inf. Technol. Control., 2013)

Evolution of efficient real-time non-linear image filters for FPGAs. - Zdenek Vasícek; Michal Bidlo; Lukás Sekanina (Soft Comput., 2013)

On Evolutionary Approximation of Logic Circuits. - Lukás Sekanina; Zdenek Vasícek (Computing with New Resources, 2014)

Cartesian genetic programming as local optimizer of logic networks. - Lukás Sekanina; Ondrej Ptak; Zdenek Vasícek (IEEE Congress on Evolutionary Computation, 2014)

Evolutionary design of approximate multipliers under different error metrics. - Zdenek Vasícek; Lukás Sekanina (DDECS, 2014)

On Evolution of Multi-category Pattern Classifiers Suitable for Embedded Systems. - Zdenek Vasícek; Michal Bidlo (EuroGP, 2014)

Acceleration of transistor-level evolution using Xilinx Zynq Platform. - Vojtech Mrazek; Zdenek Vasícek (ICES, 2014)

How to evolve complex combinational circuits from scratch? - Zdenek Vasícek; Lukás Sekanina (ICES, 2014)

Automatic Design of Low-Power VLSI Circuits: Accurate and Approximate Multipliers. - Vojtech Mrazek; Zdenek Vasícek (EUC, 2015)

Evolutionary Design of Transistor Level Digital Circuits Using Discrete Simulation. - Vojtech Mrazek; Zdenek Vasícek (EuroGP, 2015)

Cartesian GP in Optimization of Combinational Circuits with Hundreds of Inputs and Thousands of Gates. - Zdenek Vasícek (EuroGP, 2015)

Circuit Approximation Using Single- and Multi-objective Cartesian GP. - Zdenek Vasícek; Lukás Sekanina (EuroGP, 2015)

Evolutionary Approximation of Software for Embedded Systems: Median Function. - Vojtech Mrazek; Zdenek Vasícek; Lukás Sekanina (GECCO (Companion), 2015)

Evolutionary Approximation of Complex Digital Circuits. - Zdenek Vasícek; Lukás Sekanina (GECCO (Companion), 2015)

Evolutionary Approach to Approximate Digital Circuits Design. - Zdenek Vasícek; Lukás Sekanina (IEEE Trans. Evol. Comput., 2015)

Functional Equivalence Checking for Evolution of Complex Digital Circuits. - Lukás Sekanina; Zdenek Vasícek (Evolvable Hardware, 2015)

Automatic design of approximate circuits by means of multi-objective evolutionary algorithms. - Radek Hrbacek; Vojtech Mrazek; Zdenek Vasícek (DTIS, 2016)

Search-based synthesis of approximate circuits implemented into FPGAs. - Zdenek Vasícek; Lukás Sekanina (FPL, 2016)

Design of power-efficient approximate multipliers for approximate artificial neural networks. - Vojtech Mrazek; Syed Shakib Sarwar; Lukás Sekanina; Zdenek Vasícek; Kaushik Roy 001 (ICCAD, 2016)

Automatic design of arbitrary-size approximate sorting networks with error guarantee. - Vojtech Mrazek; Zdenek Vasícek (PATMOS, 2016)

Evolutionary functional approximation of circuits implemented into FPGAs. - Zdenek Vasícek; Vojtech Mrazek; Lukás Sekanina (SSCI, 2016)

Evolutionary design of complex approximate combinational circuits. - Zdenek Vasícek; Lukás Sekanina (Genet. Program. Evolvable Mach., 2016)

EvoApproxSb: Library of approximate adders and multipliers for circuit design and benchmarking of approximation methods. - Vojtech Mrazek; Radek Hrbacek; Zdenek Vasícek; Lukás Sekanina (DATE, 2017)

Towards low power approximate DCT architecture for HEVC standard. - Zdenek Vasícek; Vojtech Mrazek; Lukás Sekanina (DATE, 2017)

Parallel optimization of transistor level circuits using cartesian genetic programming. - Vojtech Mrazek; Zdenek Vasícek (GECCO (Companion), 2017)

Approximating complex arithmetic circuits with formal error guarantees: 32-bit multipliers accomplished. - Milan Ceska 002; Jirí Matyás; Vojtech Mrazek; Lukás Sekanina; Zdenek Vasícek; Tomás Vojnar (ICCAD, 2017)

Adaptive and Energy-Efficient Architectures for Machine Learning: Challenges, Opportunities, and Research Roadmap. - Muhammad Shafique 001; Rehan Hafiz; Muhammad Usama Javed; Sarmad Abbas; Lukás Sekanina; Zdenek Vasícek; Vojtech Mrazek (ISVLSI, 2017)

Trading between quality and non-functional properties of median filter in embedded systems. - Zdenek Vasícek; Vojtech Mrazek (Genet. Program. Evolvable Mach., 2017)

Design of Quality-Configurable Approximate Multipliers Suitable for Dynamic Environment. - Vojtech Mrazek; Zdenek Vasícek; Lukás Sekanina (AHS, 2018)

ADAC: Automated Design of Approximate Circuits. - Milan Ceska 002; Jirí Matyás; Vojtech Mrazek; Lukás Sekanina; Zdenek Vasícek; Tomás Vojnar (CAV (1), 2018)

Evolving boolean functions for fast and efficient randomness testing. - Vojtech Mrazek; Marek Sýs; Zdenek Vasícek; Lukás Sekanina; Vashek Matyas (GECCO, 2018)

Evolutionary design of large approximate adders optimized for various error criteria. - Vojtech Mrazek; Zdenek Vasícek (GECCO (Companion), 2018)

Design Space Exploration for Approximate Implementations of Arithmetic Data Path Primitives. - Lukás Sekanina; Vojtech Mrazek; Zdenek Vasícek (ICECS, 2018)

Special session: How approximate computing impacts verification, test and reliability. - Lukás Sekanina; Zdenek Vasícek; Alberto Bosio; Marcello Traiola; Paolo Rech; Daniel Oliveira 002; Fernando Fernandes 001; Stefano Di Carlo (VTS, 2018)

Role of circuit representation in evolutionary design of energy-efficient approximate circuits. - Vojtech Mrazek; Zdenek Vasícek; Radek Hrbacek (IET Comput. Digit. Tech., 2018)

Scalable Construction of Approximate Multipliers With Formally Guaranteed Worst Case Error. - Vojtech Mrazek; Zdenek Vasícek; Lukás Sekanina; Honglan Jiang; Jie Han 001 (IEEE Trans. Very Large Scale Integr. Syst., 2018)

Automated Search-Based Functional Approximation for Digital Circuits. - Lukás Sekanina; Zdenek Vasícek; Vojtech Mrazek (Approximate Circuits, 2019)

autoAx: An Automatic Design Space Exploration and Circuit Building Methodology utilizing Libraries of Approximate Components. - Vojtech Mrazek; Muhammad Abdullah Hanif; Zdenek Vasícek; Lukás Sekanina; Muhammad Shafique 001 (DAC, 2019)

Automated Circuit Approximation Method Driven by Data Distribution. - Zdenek Vasícek; Vojtech Mrazek; Lukás Sekanina (DATE, 2019)

Towards a Scalable EA-Based Optimization of Digital Circuits. - Jitka Kocnová; Zdenek Vasícek (EuroGP, 2019)

Impact of subcircuit selection on the efficiency of CGP-based optimization of gate-level circuits. - Jitka Kocnová; Zdenek Vasícek (GECCO (Companion), 2019)

ALWANN: Automatic Layer-Wise Approximation of Deep Neural Network Accelerators without Retraining. - Vojtech Mrazek; Zdenek Vasícek; Lukás Sekanina; Muhammad Abdullah Hanif; Muhammad Shafique 001 (ICCAD, 2019)

EA-Based Refactoring of Mapped Logic Circuits. - Jitka Kocnová; Zdenek Vasícek (ISCAS, 2019)

Formal Methods for Exact Analysis of Approximate Circuits. - Zdenek Vasícek (IEEE Access, 2019)

Using Libraries of Approximate Circuits in Design of Hardware Accelerators of Deep Neural Networks. - Vojtech Mrazek; Lukás Sekanina; Zdenek Vasícek (AICAS, 2020)

ApproxFPGAs: Embracing ASIC-Based Approximate Arithmetic Components for FPGA-Based Systems. - Bharath Srinivas Prabakaran; Vojtech Mrazek; Zdenek Vasícek; Lukás Sekanina; Muhammad Shafique 001 (DAC, 2020)

TFApprox: Towards a Fast Emulation of DNN Approximate Hardware Accelerators on GPU. - Filip Vaverka; Vojtech Mrazek; Zdenek Vasícek; Lukás Sekanina (DATE, 2020)

Design, Verification, Test and In-Field Implications of Approximate Computing Systems. - Alberto Bosio; Stefano Di Carlo; Patrick Girard 001; Ernesto Sánchez 001; Alessandro Savino; Lukás Sekanina; Marcello Traiola; Zdenek Vasícek; Arnaud Virazel (ETS, 2020)

Adaptive verifiability-driven strategy for evolutionary approximation of arithmetic circuits. - Milan Ceska 002; Jirí Matyás; Vojtech Mrazek; Lukás Sekanina; Zdenek Vasícek; Tomás Vojnar (Appl. Soft Comput., 2020)

Libraries of Approximate Circuits: Automated Design and Application in CNN Accelerators. - Vojtech Mrazek; Lukás Sekanina; Zdenek Vasícek (IEEE J. Emerg. Sel. Topics Circuits Syst., 2020)

EA-based resynthesis: an efficient tool for optimization of digital circuits. - Jitka Kocnová; Zdenek Vasícek (Genet. Program. Evolvable Mach., 2020)

Improving the Accuracy and Hardware Efficiency of Neural Networks Using Approximate Multipliers. - Mohammad Saeed Ansari; Vojtech Mrazek; Bruce F. Cockburn; Lukás Sekanina; Zdenek Vasícek; Jie Han 001 (IEEE Trans. Very Large Scale Integr. Syst., 2020)

Synthesis of approximate circuits for LUT-based FPGAs. - Zdenek Vasícek (DDECS, 2021)

Resynthesis of logic circuits using machine learning and reconvergent paths. - Jitka Kocnová; Zdenek Vasícek (DSD, 2021)

Semantically-oriented mutation operator in cartesian genetic programming for evolutionary circuit design. - David Hodan; Vojtech Mrazek; Zdenek Vasícek (Genet. Program. Evolvable Mach., 2021)

Graph-based genetic programming. - Roman Kalkreuth; Léo Françoso Dal Piccol Sotto; Zdenek Vasícek (GECCO Companion, 2022)

Delay-aware evolutionary optimization of digital circuits. - Jitka Kocnová; Zdenek Vasícek (ISVLSI, 2022)

SagTree: Towards efficient mutation in evolutionary circuit approximation. - Milan Ceska 002; Jirí Matyás; Vojtech Mrazek; Lukás Sekanina; Zdenek Vasícek; Tomás Vojnar (Swarm Evol. Comput., 2022)

General Boolean Function Benchmark Suite. - Roman Kalkreuth; Zdenek Vasícek; Jakub Husa; Diederick Vermetten; Furong Ye; Thomas Bäck (FOGA, 2023)

Towards a General Boolean Function Benchmark Suite. - Roman Kalkreuth; Zdenek Vasícek; Jakub Husa; Diederick Vermetten; Furong Ye; Thomas Bäck (GECCO Companion, 2023)

Xel-FPGAs: An End-to-End Automated Exploration Framework for Approximate Accelerators in FPGA-Based Systems. - Bharath Srinivas Prabakaran; Vojtech Mrazek; Zdenek Vasícek; Lukás Sekanina; Muhammad Shafique 001 (ICCAD, 2023)

autoXFPGAs: An End-to-End Automated Exploration Framework for Approximate Accelerators in FPGA-Based Systems. - Bharath Srinivas Prabakaran; Vojtech Mrazek; Zdenek Vasícek; Lukás Sekanina; Muhammad Shafique 001 (CoRR, 2023)

Acceleration Techniques for Automated Design of Approximate Convolutional Neural Networks. - Michal Pinos; Vojtech Mrazek; Filip Vaverka; Zdenek Vasícek; Lukás Sekanina (IEEE J. Emerg. Sel. Topics Circuits Syst., 2023)

Automated Synthesis of Commutative Approximate Arithmetic Operators. - Zdenek Vasícek (CEC, 2024)

Automated Verifiability-Driven Design of Approximate Circuits: Exploiting Error Analysis. - Zdenek Vasícek; Vojtech Mrazek; Lukás Sekanina (DATE, 2024)

Exploring Quantization and Mapping Synergy in Hardware-Aware Deep Neural Network Accelerators. - Jan Klhufek; Miroslav Safar; Vojtech Mrazek; Zdenek Vasícek; Lukás Sekanina (DDECS, 2024)

Evolutionary Approximation of Ternary Neurons for On-sensor Printed Neural Networks. - Vojtech Mrazek; Argyris Kokkinis; Panagiotis Papanikolaou; Zdenek Vasícek; Kostas Siozios; Georgios Tzimpragos; Mehdi B. Tahoori; Georgios Zervakis 001 (ICCAD, 2024)

AxMED: Formal Analysis and Automated Design of Approximate Median Filters using BDDs. - Vojtech Mrazek; Zdenek Vasícek (ISCAS, 2025)

TinyverseGP: Towards a Modular Cross-domain Benchmarking Framework for Genetic Programming. - Roman Kalkreuth; Fabrício Olivetti de França; Julian Dierkes; Marie Anastacio; Anja Jankovic 003; Zdenek Vasícek; Holger H. Hoos (CoRR, 2025)