Objective Measurement of Spatial Audio Coding Quality Based on MNLR Mapping Model. - Jing Wang 037; Xin Liu; Zedong Wang; Zhikun Wu; Xiang Xie; Zesong Fei; Jingming Kuang 001 (IIH-MSP, 2015)

Structural and functional connectivity mapping of the human corpus callosum organization with white-matter functional networks. - Pan Wang; Jianlin Wang; Qin Tang; Tara L. Alvarez; Zedong Wang; Yi-Chia Kung; Ching-Po Lin; Huafu Chen; Chun Meng; Bharat B. Biswal (NeuroImage, 2021)

Trusted Outsourced Computing Framework for Smart Contract of Permissioned Blockchain. - Wensheng Tian; Zhichao Yan; Zedong Wang; Weitao Dai; Panpan Tang; Lei Zhang (SmartWorld/UIC/ScalCom/DigitalTwin/PriComp/Meta, 2022)

OpenMixup: Open Mixup Toolbox and Benchmark for Visual Representation Learning. - Siyuan Li 002; Zedong Wang; Zicheng Liu 006; Di Wu 057; Stan Z. Li (CoRR, 2022)

Efficient Multi-order Gated Aggregation Network. - Siyuan Li 002; Zedong Wang; Zicheng Liu 006; Cheng Tan 012; Haitao Lin; Di Wu 057; Zhiyuan Chen 008; Jiangbin Zheng 002; Stan Z. Li (CoRR, 2022)

OpenSTL: A Comprehensive Benchmark of Spatio-Temporal Predictive Learning. - Cheng Tan 012; Siyuan Li 002; Zhangyang Gao; Wenfei Guan; Zedong Wang; Zicheng Liu 006; Lirong Wu; Stan Z. Li (NeurIPS, 2023)

WBRP: Consensus Algorithm Based on Weak Proof of Work. - Jiarui Li; Dongbin Wang; Hui Zhi; Wencheng Zhu; Jianing Li; Zedong Wang (Blockchain, 2024)

An Injection-Locked Clock Multiplier with Adaptive Pulsewidth Adjustment and Phase Error Cancellation Achieving 43.9fs RMS Jitter and -255.5dB FoM. - Yu He; Xuqiang Zhenq; Zedong Wang; Zunsong Yanq; Hua Xu; Fangxu Lv; Mingche Lai; Xinyu Liu (CICC, 2024)

SemiReward: A General Reward Model for Semi-supervised Learning. - Siyuan Li 002; Weiyang Jin; Zedong Wang; Fang Wu 002; Zicheng Liu 006; Cheng Tan 012; Stan Z. Li (ICLR, 2024)

MogaNet: Multi-order Gated Aggregation Network. - Siyuan Li 002; Zedong Wang; Zicheng Liu 006; Cheng Tan 012; Haitao Lin; Di Wu 057; Zhiyuan Chen 008; Jiangbin Zheng 002; Stan Z. Li (ICLR, 2024)

Short-Long Convolutions Help Hardware-Efficient Linear Attention to Focus on Long Sequences. - Zicheng Liu 006; Siyuan Li 002; Li Wang; Zedong Wang; Yunfan Liu 002; Stan Z. Li (ICML, 2024)

VQDNA: Unleashing the Power of Vector Quantization for Multi-Species Genomic Sequence Modeling. - Siyuan Li 002; Zedong Wang; Zicheng Liu 006; Di Wu 057; Cheng Tan 012; Jiangbin Zheng 002; Yufei Huang 002; Stan Z. Li (ICML, 2024)

LongVQ: Long Sequence Modeling with Vector Quantization on Structured Memory. - Zicheng Liu 006; Li Wang; Siyuan Li 002; Zedong Wang; Haitao Lin; Stan Z. Li (IJCAI, 2024)

Masked Modeling for Self-supervised Representation Learning on Vision and Beyond. - Siyuan Li 002; Luyuan Zhang; Zedong Wang; Di Wu 057; Lirong Wu; Zicheng Liu 006; Jun Xia 001; Cheng Tan 012; Yang Liu 356; Baigui Sun; Stan Z. Li (CoRR, 2024)

Switch EMA: A Free Lunch for Better Flatness and Sharpness. - Siyuan Li 002; Zicheng Liu 006; Juanxi Tian; Ge Wang; Zedong Wang; Weiyang Jin; Di Wu 057; Cheng Tan 012; Tao Lin; Yang Liu 356; Baigui Sun; Stan Z. Li (CoRR, 2024)

A Survey on Mixup Augmentations and Beyond. - Xin Jin; Hongyu Zhu; Siyuan Li 002; Zedong Wang; Zicheng Liu 006; Chang Yu 001; Huafeng Qin; Stan Z. Li (CoRR, 2024)

Unveiling the Backbone-Optimizer Coupling Bias in Visual Representation Learning. - Siyuan Li 002; Juanxi Tian; Zedong Wang; Luyuan Zhang; Zicheng Liu 006; Weiyang Jin; Yang Liu 356; Baigui Sun; Stan Z. Li (CoRR, 2024)

A 200-Gb/s 70-GHz-bandwidth 2:1 analog multiplexer in 130-nm SiGe BiCMOS process. - Sijie Fan; Zedong Wang; Hua Xu; Hengyu Xu; Wenxiang Zhen; Xuqiang Zheng (IEICE Electron. Express, 2024)

A high-output-swing 64-Gb/s PAM-4 transmitter with a 4-tap hybrid FFE in 28-nm CMOS. - Hua Xu; Xuqiang Zheng; Zedong Wang; Chen Cai; Wenxiang Zhen; Guojun Yuan; Qinfen Hao; Xuan Guo; Zhi Jin (IEICE Electron. Express, 2024)

A Deep Learning Method for Bearing Cross-Domain Fault Diagnostics Based on the Standard Envelope Spectrum. - Lubin Zhai; Xiufeng Wang; Zeyiwen Si; Zedong Wang (Sensors, 2024)

Prior-guided Hierarchical Harmonization Network for Efficient Image Dehazing. - Xiongfei Su; Siyuan Li; Yuning Cui 001; Miao Cao; Yulun Zhang 001; Zheng Chen 014; Zongliang Wu; Zedong Wang; Yuanlong Zhang; Xin Yuan 002 (AAAI, 2025)

Taming LLMs with Gradient Grouping. - Siyuan Li 002; Juanxi Tian; Zedong Wang; Xin Jin; Zicheng Liu 006; Wentao Zhang; Dan Xu (ACL (1), 2025)

MergeVQ: A Unified Framework for Visual Generation and Representation with Disentangled Token Merging and Quantization. - Siyuan Li 002; Luyuan Zhang; Zedong Wang; Juanxi Tian; Cheng Tan 012; Zicheng Liu 006; Chang Yu 001; Qingsong Xie; Haonan Lu; Haoqian Wang; Zhen Lei 001 (CVPR, 2025)

A 25 Gb/s 5.99 pJ/bit SerDes receiver with CTLE and quarter-rate adaptive loop-unrolling 5-tap DFE in 28-nm CMOS technology for wireline medium-reach interconnection. - Zhaoyang Liu; Bao Chen; Zhanhao Wen; Xuqiang Zheng; Zedong Wang; Jiang Xu; Wenxiang Zhen (IEICE Electron. Express, 2025)

A dual-channel half-rate 32 Gb/s, 5.3 pJ/bit SerDes transceiver with 3-tap-FFE and CTLE in 28-nm CMOS for very short reach C2C and C2M interconnection. - Zhaoyang Liu; Zhanhao Wen; Bao Chen; Jiang Xu; Zedong Wang; Xuqiang Zheng (Microelectron. J., 2025)

A Low-Jitter and Low-Reference-Spur Ring-VCO-Based Injection-Locked Clock Multiplier Utilizing a Complementary-Injection Scheme and an Adaptive Pulsewidth Adjustment. - Zedong Wang; Xuqiang Zheng; Yu He; Hua Xu; Sai Li; Zunsong Yang; Fangxu Lv; Mingche Lai; Xinyu Liu 004 (IEEE J. Solid State Circuits, 2025)

Taming LLMs by Scaling Learning Rates with Gradient Grouping. - Siyuan Li 002; Juanxi Tian; Zedong Wang; Xin Jin; Zicheng Liu 006; Wentao Zhang; Dan Xu (CoRR, 2025)

Rep-MTL: Unleashing the Power of Representation-level Task Saliency for Multi-Task Learning. - Zedong Wang; Siyuan Li 002; Dan Xu (CoRR, 2025)

A 112-Gb/s PAM-4 Retimer Transceiver With Jitter-Filtering Clocking Scheme and BER Optimization Technique in 28-nm CMOS. - Hua Xu; Mingche Lai; Xuqiang Zheng; Zedong Wang; Jiang Xu; Sai Li; Fangxu Lv; Min Liu; Weijie Li; Zhanhao Wen; Xuan Guo; Xinhua Wang; et al. (IEEE J. Solid State Circuits, 2025)