A Low Jitter Double-Tailed Strong-Arm Latch Based Digital-to-Time Converter (DTC). - Zeeshan Ali 005; Makwana Harshit R; Shalabh Gupta (ICECS, 2020)

A Fast Settling Fractional-N DPLL With Loop-Order Switching. - Pallavi Paliwal; Vivek Yadav; Zeeshan Ali 005; Shalabh Gupta (IEEE Trans. Very Large Scale Integr. Syst., 2020)

A Fast Locking Ring Oscillator Based Fractional-N DPLL With an Assistance From a LUT-Based FSM. - Zeeshan Ali 005; Pallavi Paliwal; Rupesh Lad; Dhanraj Bhukya; Shalabh Gupta (ISCAS, 2022)

Stability Analysis for Fast Settling Switched Digital Phase-Locked Loops (DPLLs). - Zeeshan Ali 005; Pallavi Paliwal; Phani Raj; Deepak Anand; Debasattam Pal; Shalabh Gupta (IEEE Control. Syst. Lett., 2023)

Impact of Receiver Thermal Noise and PLL RMS Jitter in Radar Measurements. - Zeeshan Ali 005; Mostafa Elsayed; Girish Tiwari; Meraj Ahmad; Julien Le Kernec; Hadi Heidari; Shalabh Gupta (IEEE Trans. Instrum. Meas., 2024)

Cryo-CMOS 0.432mW UHF Filter for Scalable Quantum Computing in 22nm FD-SOI Technology. - Stavroula Kapoulea; Hossein Eslahi; Zeeshan Ali 005; Mohammed Waqas Mughal; Meraj Ahmad; Martin Weides; Hadi Heidari (ISCAS, 2025)

De-Embedding Methodology to Characterize Linearity of Active Filters Under Process Variations. - Hossein Eslahi; Stavroula Kapoulea; Zeeshan Ali 005; Mohammed Waqas Mughal; Farman Ullah; Meraj Ahmad; Martin Weides; Hadi Heidari (IEEE Trans. Very Large Scale Integr. Syst., 2025)