Design methodology for distributed systems. - Zeev Barzilai (1978)

VLSI Self-Testing Based on Syndrome Techniques. - Zeev Barzilai; Jacob Savir; George Markowsky; Merlin G. Smith (ITC, 1981)

The Weighted Syndrome Sums Approach to VLSI Testing. - Zeev Barzilai; Jacob Savir; George Markowsky; Merlin G. Smith (IEEE Trans. Computers, 1981)

Simulating pass transistor circuits using logic simulation machines. - Zeev Barzilai; Leendert M. Huisman; Gabriel M. Silberman; Donald T. Tang; Lin S. Woo (DAC, 1983)

Comparison of AC Self-Testing Procedures. - Zeev Barzilai; Barry K. Rosen (ITC, 1983)

Exhaustive Generation of Bit Patterns with Applications to VLSI Self-Testing. - Zeev Barzilai; Don Coppersmith; Arnold L. Rosenberg (IEEE Trans. Computers, 1983)

Fast Pass-Transistor Simulation for Custom MOS Circuits. - Zeev Barzilai; Leendert M. Huisman; Gabriel M. Silberman; Donald T. Tang; Lin S. Woo (IEEE Des. Test, 1984)

Using a Hardware Simulation Engine for Custom MOS Structured Designs. - Zeev Barzilai; Daniel K. Beece; Leendert M. Huisman; Gabriel M. Silberman (IBM J. Res. Dev., 1984)

Accurate Fault Modeling and Efficient Simulation of Differential CVS Circuits. - Zeev Barzilai; Vijay S. Iyengar; Barry K. Rosen; Gabriel M. Silberman (ITC, 1985)

SLS - a fast switch level simulator for verification and fault coverage analysis. - Zeev Barzilai; Daniel K. Beece; Leendert M. Huisman; Vijay S. Iyengar; Gabriel M. Silberman (DAC, 1986)

Efficient Fault Simulation of CMOS Circuits with Accurate Models. - Zeev Barzilai; J. Lawrence Carter; Vijay S. Iyengar; Indira Nair; Barry K. Rosen; Joe D. Rutledge; Gabriel M. Silberman (ITC, 1986)

HSS–A High-Speed Simulator. - Zeev Barzilai; J. Lawrence Carter; Barry K. Rosen; Joe D. Rutledge (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1987)

SLS-a fast switch-level simulator [for MOS]. - Zeev Barzilai; Daniel K. Beece; Leendert M. Huisman; Vijay S. Iyengar; Gabriel M. Silberman (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1988)