An efficient stream memory architecture for heterogeneous multicore processor. - Rangyu Deng; Weixia Xu; Qiang Dou; Hongwei Zhou; Zefu Dai; Haiyan Chen (ISCC, 2009)

A 1 cycle-per-byte XML parsing accelerator. - Zefu Dai; Nick Ni; Jianwen Zhu (FPGA, 2010)

Credit Borrow and Repay: Sharing DRAM with minimum latency and bandwidth guarantees. - Zefu Dai; Mark Jarvin; Jianwen Zhu (ICCAD, 2010)

A bursty multi-port memory controller with quality-of-service guarantees. - Zefu Dai; Jianwen Zhu (CODES+ISSS, 2011)

Saturating the transceiver bandwidth: switch fabric design on FPGAs. - Zefu Dai; Jianwen Zhu (FPGA, 2012)

The Virtual Open Page Buffer for Multi-core and Multi-thread Processors. - Hongwei Zhou; Rangyu Deng; Zefu Dai; Xiaobo Yan; Ying Zhang 032; Caixia Sun (HPCC/CSS/ICESS, 2014)