Current-Mode CMOS Galois Field Circuits. - Zeljko Zilic; Zvonko G. Vranesic (ISMVL, 1993)

Reed-Muller Forms for Incompletely Specified Functions via Sparse Polynomial Interpolation. - Zeljko Zilic; Zvonko G. Vranesic (ISMVL, 1995)

A Multiple-Valued Reed-Muller Transform for Incompletely Specified Functions. - Zeljko Zilic; Zvonko G. Vranesic (IEEE Trans. Computers, 1995)

Experience in Designing a Large-scale Multiprocessor using Field-Programmable Devices and Advanced CAD Tools. - Stephen Brown 003; Naraig Manjikian; Zvonko G. Vranesic; S. Caranci; A. Grbic; R. Grindley; M. Gusat; K. Loveless; Zeljko Zilic; Sinisa Srbljic (DAC, 1996)

Using BDDs to Design ULMs for FPGAs. - Zeljko Zilic; Zvonko G. Vranesic (FPGA, 1996)

New Interpolation Algorithms for Multiple-Valued Reed-Muller Forms. - Zeljko Zilic; Zvonko G. Vranesic (ISMVL, 1996)

Design and Implementation of the NUMAchine Multiprocessor. - A. Grbic; Stephen Brown 003; S. Caranci; R. Grindley; M. Gusat; Guy G. Lemieux; K. Loveless; Naraig Manjikian; Sinisa Srbljic; Michael Stumm; Zvonko G. Vranesic; Zeljko Zilic (DAC, 1998)

Using Decision Diagrams to Design ULMs for FPGAs. - Zeljko Zilic; Zvonko G. Vranesic (IEEE Trans. Computers, 1998)

On Feasible Multivariate Polynomial Interpolations over Arbitrary Fields. - Zeljko Zilic; Katarzyna Radecka (ISSAC, 1999)

Alternatives in Teaching System-Building Skills. - Zeljko Zilic (MSE, 1999)

Dynamic clock management for low power applications in FPGAs. - Ian Brynjolfson; Zeljko Zilic (CICC, 2000)

FPGA clock management for low power applications (poster abstract). - Ian Brynjolfson; Zeljko Zilic (FPGA, 2000)

The NUMAchine Multiprocessor. - R. Grindley; Tarek S. Abdelrahman; Stephen Brown 003; S. Caranci; D. DeVries; Benjamin Gamsa; A. Grbic; M. Gusat; R. Ho; Orran Krieger; Guy G. Lemieux; K. Loveless; et al. (ICPP, 2000)

Using Arithmetic Transform for Verification of Datapath Circuits via Error Modeling. - Katarzyna Radecka; Zeljko Zilic (VTS, 2000)

Arithmetic Transforms for Verifying Compositions of Sequential Datapaths. - Katarzyna Radecka; Zeljko Zilic (ICCD, 2001)

A practical substrate modeling algorithm with active guardband macromodel for mixed-signal substrate coupling verification. - Henry H. Y. Chan; Zeljko Zilic (ICECS, 2001)

New embedded memory architecture for enhanced yield, performance and power consumption. - Boris Polianskikh; Zeljko Zilic (ICECS, 2001)

Combinational verification by simulations, SAT and BDDs. - Katarzyna Radecka; Zeljko Zilic; Karim Khordoc (ICECS, 2001)

A new PLL design for clock management applications. - Ian Brynjolfson; Zeljko Zilic (ISCAS (4), 2001)

: Identifying redundant gate replacements in verification by error modeling. - Zeljko Zilic; Katarzyna Radecka (ITC, 2001)

An FPGA based move generator for the game of chess. - Marc Boule; Zeljko Zilic (CICC, 2002)

FPGA test time reduction through a novel interconnect testing scheme. - Stuart McCracken; Zeljko Zilic (FPGA, 2002)

Specifying and verifying imprecise sequential datapaths by Arithmetic Transforms. - Katarzyna Radecka; Zeljko Zilic (ICCAD, 2002)

High speed asynchronous structures for inter-clock domain communication. - Atanu Chattopadhyay; Zeljko Zilic (ICECS, 2002)

Automated SystemC to VHDL translation in hardware/software codesign. - Christian Côté; Zeljko Zilic (ICECS, 2002)

A single-rail handshake CDMA correlator. - Weiwen Zhu; Zeljko Zilic; Radu Negulescu (ICECS, 2002)

Design and Implementation of Error Detection and Correction Circuitry for Multilevel Memory Protection. - Boris Polianskikh; Zeljko Zilic (ISMVL, 2002)

The Role of Super-Fast Transforms in Speeding Up Quantum Computations. - Zeljko Zilic; Katarzyna Radecka (ISMVL, 2002)

Identifying Redundant Wire Replacements for Synthesis and Verification. - Katarzyna Radecka; Zeljko Zilic (ASP-DAC/VLSI Design, 2002)

An FPGA Move Generator for the Game of Chess. - Marc Boule; Zeljko Zilic (J. Int. Comput. Games Assoc., 2002)

A Deterministic Multivariate Interpolation Algorithm for Small Finite Fields. - Zeljko Zilic; Zvonko G. Vranesic (IEEE Trans. Computers, 2002)

Testing for bit error rate in FPGA communication interfaces. - Yongquan Fan; Zeljko Zilic (FPGA, 2003)

A globally asynchronous locally dynamic system for ASICs and SoCs. - Atanu Chattopadhyay; Zeljko Zilic (ACM Great Lakes Symposium on VLSI, 2003)

Layered Approach to Designing System Test Interfaces. - Man Wah Chiang; Zeljko Zilic (VTS, 2003)

FPGA Emulation of Quantum Circuits. - Ahmed Usman Khalid; Zeljko Zilic; Katarzyna Radecka (ICCD, 2004)

A novel scheme of implementing high speed AWGN communication channel emulators in FPGAs. - Yongquan Fan; Zeljko Zilic (ISCAS (2), 2004)

Estimating Phase-Locked Loop Jitter due to Substrate Coupling: A Cyclostationary Approach. - Henry H. Y. Chan; Zeljko Zilic (ISQED, 2004)

A Versatile High Speed Bit Error Rate Testing Scheme. - Yongquan Fan; Zeljko Zilic; Man Wah Chiang (ISQED, 2004)

Design for Testability of FPGA Blocks. - Stuart McCracken; Zeljko Zilic (ISQED, 2004)

Architectures of Increased Availability Wireless Sensor Network Nodes. - Man Wah Chiang; Zeljko Zilic; Jean-Samuel Chenard; Katarzyna Radecka (ITC, 2004)

A novel phase detector for PAM-4 clock recovery in high speed serial links. - Kahn Li Lim; Zeljko Zilic (SoCC, 2004)

Design Verification by Test Vectors and Arithmetic Transform Universal Test Set. - Katarzyna Radecka; Zeljko Zilic (IEEE Trans. Computers, 2004)

Design methodology for wireless nodes with printed antennas. - Jean-Samuel Chenard; Chun Yiu Chu; Zeljko Zilic; Milica Popovic (DAC, 2005)

Incorporating Ef.cient Assertion Checkers into Hardware Emulation. - Marc Boule; Zeljko Zilic (ICCD, 2005)

Modeling Layout Effects for Sensitivity-Based Analog Circuit Optimization. - Henry H. Y. Chan; Zeljko Zilic (ISQED, 2005)

Expandable and Robust Laboratory for Microprocessor Systems. - Jean-Samuel Chenard; Ahmed Usman Khalid; Milos Prokic; Rong Zhang; K.-L. Lim; Atanu Chattopadhyay; Zeljko Zilic (MSE, 2005)

GALDS: a complete framework for designing multiclock ASICs and SoCs. - Atanu Chattopadhyay; Zeljko Zilic (IEEE Trans. Very Large Scale Integr. Syst., 2005)

Efficient Automata-Based Assertion-Checker Synthesis of PSL Properties. - Marc Boule; Zeljko Zilic (HLDVT, 2006)

Adding Debug Enhancements to Assertion Checkers for Hardware Emulation and Silicon Debug. - Marc Boule; Jean-Samuel Chenard; Zeljko Zilic (ICCD, 2006)

Algorithms for Compositions of Arithmetic Transforms and Their Extensions. - Yu Pang; Katarzyna Radecka; Zeljko Zilic (ICECS, 2006)

Arithmetic Transforms of Imprecise Datapaths by Taylor Series Conversion. - Yu Pang; Katarzyna Radecka; Zeljko Zilic (ICECS, 2006)

An Accelerated Jitter Tolerance Test Technique on Ate for 1.5GB/S and 3GB/S Serial-ATA. - Yongquan Fan; Yi Cai; Liming Fang; Anant Verma; William Burchanowski; Zeljko Zilic; Sandeep Kumar (ITC, 2006)

Energy Efficient Software-Based Self-Test for Wireless Sensor Network Nodes. - Rong Zhang; Zeljko Zilic; Katarzyna Radecka (VTS, 2006)

Arithmetic transforms for compositions of sequential and imprecise datapaths. - Knockaert Radecka; Zeljko Zilic (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006)

Latency Reduction of Global Traffic in Wormhole-Routed Meshes Using Hierarchical Rings for Global Routing. - Stephan Bourduas; Zeljko Zilic (ASAP, 2007)

Efficient Automata-Based Assertion-Checker Synthesis of SEREs for Hardware Emulation. - Marc Boule; Zeljko Zilic (ASP-DAC, 2007)

Modeling Simultaneous Switching Noise-Induced Jitter for System-on-Chip Phase-Locked Loops. - Henry H. Y. Chan; Zeljko Zilic (DAC, 2007)

Reversible circuit technology mapping from non-reversible specifications. - Zeljko Zilic; Katarzyna Radecka; Ali Kazamiphur (DATE, 2007)

A Performance Driven Layout Compaction Optimization Algorithm for Analog Circuits. - Henry H. Y. Chan; Zeljko Zilic (ISCAS, 2007)

Reconfigurable Clock Distribution Circuitry. - Atanu Chattopadhyay; Zeljko Zilic (ISCAS, 2007)

Assertion Checkers in Verification, Silicon Debug and In-Field Diagnosis. - Marc Boule; Jean-Samuel Chenard; Zeljko Zilic (ISQED, 2007)

A high accuracy high throughput jitter test solution on ATE for 3GBPS and 6gbps serial-ata. - Yongquan Fan; Yi Cai; Zeljko Zilic (ITC, 2007)

A Laboratory for Wireless and Mobile Embedded Systems. - Zeljko Zilic; Jean-Samuel Chenard; Milos Prokic (MSE, 2007)

A Hybrid Ring/Mesh Interconnect for Network-on-Chip Using Hierarchical Rings for Global Routing. - Stephan Bourduas; Zeljko Zilic (NOCS, 2007)

Debug enhancements in assertion-checker generation. - Marc Boule; Jean-Samuel Chenard; Zeljko Zilic (IET Comput. Digit. Tech., 2007)

Scaling and Better Approximating Quantum Fourier Transform by Higher Radices. - Zeljko Zilic; Katarzyna Radecka (IEEE Trans. Computers, 2007)

Built-in Clock Skew System for On-line Debug and Repair. - Atanu Chattopadhyay; Zeljko Zilic (DATE, 2008)

Proving and disproving assertion rewrite rules with automated theorem provers. - Katell Morin-Allory; Marc Boule; Dominique Borrione; Zeljko Zilic (HLDVT, 2008)

A Quality-Driven Design Approach for NoCs. - Stephan Bourduas; Jean-Samuel Chenard; Zeljko Zilic (IEEE Des. Test Comput., 2008)

A Laboratory Setup and Teaching Methodology for Wireless and Mobile Embedded Systems. - Jean-Samuel Chenard; Zeljko Zilic; Milos Prokic (IEEE Trans. Educ., 2008)

BER Testing of Communication Interfaces. - Yongquan Fan; Zeljko Zilic (IEEE Trans. Instrum. Meas., 2008)

Automata-based assertion-checker synthesis of PSL properties. - Marc Boule; Zeljko Zilic (ACM Trans. Design Autom. Electr. Syst., 2008)

Cache line reservation: exploring a scheme for cache-friendly object allocation. - Ivan Bilicki; Vijay Sundaresan; Daryl Maier; Nikola Grcevski; Zeljko Zilic (CASCON, 2009)

Serial reconfigurable mismatch-tolerant clock distribution. - Atanu Chattopadhyay; Zeljko Zilic (DAC, 2009)

Reliability aware NoC router architecture using input channel buffer sharing. - Mohammad Hossein Neishaburi; Zeljko Zilic (ACM Great Lakes Symposium on VLSI, 2009)

MYGEN: automata-based on-line test generator for assertion-based verification. - Yann Oddos; Katell Morin-Allory; Dominique Borrione; Marc Boule; Zeljko Zilic (ACM Great Lakes Symposium on VLSI, 2009)

A versatile scheme for the validation, testing and debugging of High Speed Serial Interfaces. - Yongquan Fan; Zeljko Zilic (HLDVT, 2009)

Airwolf-TG: A test generator for assertion-based dynamic verification. - Jason G. Tong; Marc Boule; Zeljko Zilic (HLDVT, 2009)

Designing and Using FPGAs beyond Classical Binary Logic: Opportunities in Nano-Scale Integration Age. - Zeljko Zilic (ISMVL, 2009)

Accelerating jitter tolerance qualification for high speed serial interfaces. - Yongquan Fan; Zeljko Zilic (ISQED, 2009)

Enabling efficient post-silicon debug by clustering of hardware-assertions. - Mohammad Hossein Neishaburi; Zeljko Zilic (DATE, 2010)

Direct residue-to-analog conversion scheme based on Chinese Remainder Theorem. - Omar Abdelfattah; Andraws I. Swidan; Zeljko Zilic (ICECS, 2010)

An efficient method to perform range analysis for DSP circuits. - Yu Pang; Katarzyna Radecka; Zeljko Zilic (ICECS, 2010)

Qualifying Serial Interface Jitter Rapidly and Cost-effectively. - Yongquan Fan; Zeljko Zilic (J. Electron. Test., 2010)

Defining and Providing Coverage for Assertion-Based Dynamic Verification. - Jason G. Tong; Marc Boule; Zeljko Zilic (J. Electron. Test., 2010)

Validating Assertion Language Rewrite Rules and Semantics With Automated Theorem Provers. - Katell Morin-Allory; Marc Boule; Dominique Borrione; Zeljko Zilic (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2010)

Optimization of Imprecise Circuits Represented by Taylor Series and Real-Valued Polynomials. - Yu Pang; Katarzyna Radecka; Zeljko Zilic (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2010)

An efficient hybrid engine to perform range analysis and allocate integer bit-widths for arithmetic circuits. - Yu Pang; Katarzyna Radecka; Zeljko Zilic (ASP-DAC, 2011)

Hierarchical Embedded Logic Analyzer for Accurate Root-Cause Analysis. - Mohammad Hossein Neishaburi; Zeljko Zilic (DFT, 2011)

Debug Aware AXI-based Network Interface. - Mohammad Hossein Neishaburi; Zeljko Zilic (DFT, 2011)

On Failure Rate Assessment Using an Executable Model of the System. - Mohammad Hossein Neishaburi; Zeljko Zilic (DSD, 2011)

Real-time address trace compression for emulated and real system-on-chip processor core debugging. - Bojan Mihajlovic; Zeljko Zilic (ACM Great Lakes Symposium on VLSI, 2011)

ERAVC: Enhanced reliability aware NoC router. - Mohammad Hossein Neishaburi; Zeljko Zilic (ISQED, 2011)

Teaching for evolution towards embedded multi-sensor interfaces. - Zeljko Zilic; Boris Karajica (MSE, 2011)

High-level design of integrated microsystems - arithmetic perspective. - Zeljko Zilic; Boris Karajica (ROSE, 2011)

A distributed AXI-based platform for post-silicon validation. - Mohammad Hossein Neishaburi; Zeljko Zilic (VTS, 2011)

Fault tolerant glucose sensor readout and recalibration. - Zeljko Zilic; Katarzyna Radecka (Wireless Health, 2011)

Guest Editors' Introduction: Multicore SoC Validation with Transaction-Level Models. - Prabhat Mishra 001; Zeljko Zilic; Sandeep K. Shukla (IEEE Des. Test Comput., 2011)

A Brief History of Multiprocessors and EDA. - Sandeep K. Shukla; Prabhat Mishra 001; Zeljko Zilic (IEEE Des. Test Comput., 2011)

Challenges of Rapidly Emerging Consumer Space Multiprocessors. - Zeljko Zilic; Prabhat Mishra 001; Sandeep K. Shukla (IEEE Des. Test Comput., 2011)

Modeling and evaluation of ring-based interconnects for Network-on-Chip. - Stephan Bourduas; Zeljko Zilic (J. Syst. Archit., 2011)

MSE minimization and fault-tolerant data fusion for multi-sensor systems. - Atena Roshan Fekr; Majid Janidarmian; Omid Sarbishei; Benjamin Nahill; Katarzyna Radecka; Zeljko Zilic (ICCD, 2012)

Issues in Multi-valued Multi-modal Sensor Fusion. - Majid Janidarmian; Zeljko Zilic; Katarzyna Radecka (ISMVL, 2012)

An enhanced debug-aware network interface for Network-on-Chip. - Mohammad Hossein Neishaburi; Zeljko Zilic (ISQED, 2012)

Assertion clustering for compacted test sequence generation. - Jason G. Tong; Marc Bottle; Zeljko Zilic (ISQED, 2012)

Building Blocks to Use in Innovative Non-volatile FPGA Architecture Based on MTJs. - Luca Montesi; Zeljko Zilic; Takahiro Hanyu; Daisuke Suzuki (ISVLSI, 2012)

Oversampled multi-phase time-domain bit-error rate processing for transmitter testing. - Rozita Najafi; Carle Banville; Mohamed Hafed; Zeljko Zilic (NEWCAS, 2012)

An FPGA implementation for a high-speed optical link with a PCIe interface. - Edin Kadric; Naraig Manjikian; Zeljko Zilic (SoCC, 2012)

An infrastructure for debug using clusters of assertion-checkers. - Mohammad Hossein Neishaburi; Zeljko Zilic (Microelectron. Reliab., 2012)

Analytical Optimization of Bit-Widths in Fixed-Point LTI Systems. - Omid Sarbishei; Katarzyna Radecka; Zeljko Zilic (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2012)

Flexible and Reconfigurable Mismatch-Tolerant Serial Clock Distribution Networks. - Atanu Chattopadhyay; Zeljko Zilic (IEEE Trans. Very Large Scale Integr. Syst., 2012)

SAR Computation and Channel Modeling of Body Area Network. - Yu Pang; Qian Lei; Jinzhao Lin; Zhiyong Luo; Zhangyong Li; Zeljko Zilic; Katarzyna Radecka (BODYNETS, 2013)

An efficient fault-tolerant sensor fusion algorithm for accelerometers. - Omid Sarbishei; Benjamin Nahill; Atena Roshan Fekr; Majid Janidarmian; Katarzyna Radecka; Zeljko Zilic; Boris Karajica (BSN, 2013)

Tutorial: Methodologies and tools for embedded multisensory systems based on ARM cortex M processors. - Zeljko Zilic (CASES, 2013)

An FPGA implementation of wait-free data synchronization protocols. - Benjamin Nahill; Ari Ramdial; Haibo Zeng 001; Marco Di Natale; Zeljko Zilic (ETFA, 2013)

Efficient Data Encoding for Improving Fault Simulation Performance on GPUs. - Jason G. Tong; Marc Boule; Zeljko Zilic (ISED, 2013)

Managing the microprocessor course scope expansion. - Ashraf Suyyagh; Benjamin Nahill; Alexandre Courtemanche; Evgeny Kirshin; Zeljko Zilic; Boris Karajica (MSE, 2013)

A Fault Tolerant Hierarchical Network on Chip Router Architecture. - Mohammad Hossein Neishaburi; Zeljko Zilic (J. Electron. Test., 2013)

NISHA: A fault-tolerant NoC router enabling deadlock-free Interconnection of Subnets in Hierarchical Architectures. - Mohammad Hossein Neishaburi; Zeljko Zilic (J. Syst. Archit., 2013)

"Quantum Circuit Simulations" by G. F. Viamontes, I. L. Markov and J. P. Hayes. - Zeljko Zilic (Quantum Inf. Process., 2013)

Test compaction techniques for assertion-based test generation. - Jason G. Tong; Marc Boule; Zeljko Zilic (ACM Trans. Design Autom. Electr. Syst., 2013)

Design of an e-Health Respiration and Body Posture Monitoring System and Its Application for Rib Cage and Abdomen Synchrony Analysis. - Atena Roshan Fekr; Katarzyna Radecka; Zeljko Zilic (BIBE, 2014)

Linear regression techniques for efficient analysis of transistor variability. - Dimitrios Stamoulis; Dimitrios Rodopoulos; Brett H. Meyer; Dimitrios Soudris; Zeljko Zilic (ICECS, 2014)

Multi-sensor blind recalibration in mHealth applications. - Atena Roshan Fekr; Majid Janidarmian; Katarzyna Radecka; Zeljko Zilic (IHTC, 2014)

Affordable erehabilitation monitoring platform. - Majid Janidarmian; Atena Roshan Fekr; Katarzyna Radecka; Zeljko Zilic (IHTC, 2014)

Development of a Remote Monitoring System for Respiratory Analysis. - Atena Roshan Fekr; Majid Janidarmian; Katarzyna Radecka; Zeljko Zilic (IoT360 (1), 2014)

Tidal volume variability and respiration rate estimation using a wearable accelerometer sensor. - Atena Roshan Fekr; Katarzyna Radecka; Zeljko Zilic (MobiHealth, 2014)

Automated diagnosis of knee pathology using sensory data. - Majid Janidarmian; Katarzyna Radecka; Zeljko Zilic (MobiHealth, 2014)

A hybrid arithmetic transform for precision analysis of floating-point polynomial specifications. - Omid Sarbishei; Katarzyna Radecka; Zeljko Zilic (NEWCAS, 2014)

A Medical Cloud-Based Platform for Respiration Rate Measurement and Hierarchical Classification of Breath Disorders. - Atena Roshan Fekr; Majid Janidarmian; Katarzyna Radecka; Zeljko Zilic (Sensors, 2014)

On a New Mechanism of Trigger Generation for Post-Silicon Debugging. - Mohammad Hossein Neishaburi; Zeljko Zilic (IEEE Trans. Computers, 2014)

Dynamically Instrumenting the QEMU Emulator for Linux Process Trace Generation with the GDB Debugger. - Bojan Mihajlovic; Zeljko Zilic; Warren J. Gross (ACM Trans. Embed. Comput. Syst., 2014)

FLogFS: A lightweight flash log file system. - Benjamin Nahill; Zeljko Zilic (BSN, 2015)

Efficient Reliability Analysis of Processor Datapath using Atomistic BTI Variability Models. - Dimitrios Stamoulis; Dimitrios Rodopoulos; Brett H. Meyer; Dimitrios Soudris; Francky Catthoor; Zeljko Zilic (ACM Great Lakes Symposium on VLSI, 2015)

System on chip failure rate assessment using the executable model of a system. - Mohammad Hossein Neishaburi; Zeljko Zilic (Computing, 2015)

Movement analysis of the chest compartments and a real-time quality feedback during breathing therapy. - Atena Roshan Fekr; Majid Janidarmian; Katarzyna Radecka; Zeljko Zilic (Netw. Model. Anal. Health Informatics Bioinform., 2015)

Architecture-Aware Real-Time Compression of Execution Traces. - Bojan Mihajlovic; Zeljko Zilic; Warren J. Gross (ACM Trans. Embed. Comput. Syst., 2015)

Design and Evaluation of an Intelligent Remote Tidal Volume Variability Monitoring System in E-Health Applications. - Atena Roshan Fekr; Katarzyna Radecka; Zeljko Zilic (IEEE J. Biomed. Health Informatics, 2015)

Haptic feedback and human performance in a wearable sensor system. - Majid Janidarmian; Atena Roshan Fekr; Katarzyna Radecka; Zeljko Zilic (BHI, 2016)

ECG compression for mobile sensor platforms. - Yi Steven Ding; Zeljko Zilic (BSN, 2016)

Mobility and Direction Aware Ad-hoc on Demand Distance Vector Routing Protocol. - Andraws I. Swidan; Haytham Bani Abdelghany; Ramzi R. Saifan; Zeljko Zilic (FNC/MobiSPC, 2016)

Capturing True Workload Dependency of BTI-induced Degradation in CPU Components. - Dimitrios Stamoulis; Simone Corbetta; Dimitrios Rodopoulos; Pieter Weckx; Peter Debacker; Brett H. Meyer; Ben Kaczer; Praveen Raghavan; Dimitrios Soudris; Francky Catthoor; Zeljko Zilic (ACM Great Lakes Symposium on VLSI, 2016)

Accelerating assertion assessment using GPUs. - Jason G. Tong; Marc Boule; Zeljko Zilic (HLDVT, 2016)

Enabling Debug in IoT Wireless Development and Deployment with Security Considerations. - Amirhossein Shahshahani; Andrey Tolstikhin; Zeljko Zilic (NATW, 2016)

Design of a modeling and validation platform for closed loop glucose control. - Ari J. G. Ramdial; Zeljko Zilic (SummerSim, 2016)

Adaptive parametric tuning of glucose-insulin kinetics models using multilayer perceptrons. - Ari J. G. Ramdial; Zeljko Zilic (SummerSim, 2016)

Respiration Disorders Classification With Informative Features for m-Health Applications. - Atena Roshan Fekr; Majid Janidarmian; Katarzyna Radecka; Zeljko Zilic (IEEE J. Biomed. Health Informatics, 2016)

Evaluation of an RF wearable device for non-invasive real-time hydration monitoring. - Junchao Wang; Zeljko Zilic; Yutian Shu (BSN, 2017)

Concealed regression for aggregation in low power wireless networks. - Andrey Tolstikhin; Zeljko Zilic (ICIN, 2017)

Ultrasound sensors and its application in human heart rate monitoring. - Amirhossein Shahshahani; Davood Raeisi Nafchi; Zeljko Zilic (ISCAS, 2017)

Designing and Evaluating a Vibrotactile Language for Sensory Substitution Systems. - Majid Janidarmian; Atena Roshan Fekr; Katarzyna Radecka; Zeljko Zilic (MobiHealth, 2017)

A Novel Algorithm to Reduce Machine Learning Efforts in Real-Time Sensor Data Analysis. - Majid Janidarmian; Atena Roshan Fekr; Katarzyna Radecka; Zeljko Zilic (MobiHealth, 2017)

A Comprehensive Analysis on Wearable Acceleration Sensors in Human Activity Recognition. - Majid Janidarmian; Atena Roshan Fekr; Katarzyna Radecka; Zeljko Zilic (Sensors, 2017)

Software Defined Radio-Based Testbed for Wireless Body Area Network. - Zhiyu Chen; Junchao Wang; Kaining Han; Zeljko Zilic (BIBE, 2018)

Implementation and Analysis of Spin-Torque-Based Reversible D-Latch. - Anant Aravind Kulkarni; Brajesh Kumar Kaushik; Zeljko Zilic (CCECE, 2018)

Ultrasound Based Respiratory Monitoring Evaluation Under Human Body Motions. - Amirhossein Shahshahani; Sharmistha Bhadra; Zeljko Zilic (IEEE SENSORS, 2018)

A Continuous Respiratory Monitoring System Using Ultrasound Piezo Transducer. - Amirhossein Shahshahani; Sharmistha Bhadra; Zeljko Zilic (ISCAS, 2018)

An ASIC Implementation of Security Scheme for Body Area Networks. - Junchao Wang; Kaining Han; Anastasios Alexandridis; Zeljko Zilic; Yu Pang; Jinzhao Lin (ISCAS, 2018)

Area and Energy Efficient Magnetic Full Adder based on Differential Spin Hall MRAM. - Sanjay Prajapati; Zeljko Zilic; Brajesh Kumar Kaushik (NEWCAS, 2018)

Using the Characteristic Value of the Body Channel for Encryption of Body Area Networks. - Junchao Wang; Kaining Han; Anastasios Alexandridis; Zeljko Zilic; Tong Bai; Jinzhao Lin; Yu Pang; Guoquan Li (NEWCAS, 2018)

Multi-point Security by a Multiplatform-compatible Multifunctional Authentication and Encryption Board. - Ravdeep Singh Boparai; Anastasios Alexandridis; Zeljko Zilic (J. Comput. Inf. Technol., 2018)

A novel security scheme for Body Area Networks compatible with smart vehicles. - Junchao Wang; Kaining Han; Anastasios Alexandridis; Zeljko Zilic; Yu Pang; Wei Wu 002; Sadia Din; Gwanggil Jeon (Comput. Networks, 2018)

Protocol with self-adaptive GB for BANs. - Tong Bai; Jinzhao Lin; Yu Pang; Guoquan Li; Zhangyong Li; Huiqian Wang; Junchao Wang; Zeljko Zilic (IET Commun., 2018)

Ultrasound Sensors for Diaphragm Motion Tracking: An Application in Non-Invasive Respiratory Monitoring. - Amirhossein Shahshahani; Carl Laverdiere; Sharmistha Bhadra; Zeljko Zilic (Sensors, 2018)

A Software Defined Radio Evaluation Platform for WBAN Systems. - Junchao Wang; Kaining Han; Zhiyu Chen; Anastasios Alexandridis; Zeljko Zilic; Yu Pang; Jinzhao Lin (Sensors, 2018)

An Encryption Method for BAN Using the Channel Characteristics. - Liangguang Peng; Jinzhao Lin; Tong Bai; Yu Pang; Guoquan Li; Huiquan Wang; Xiaoming Jiang; Junchao Wang; Zeljko Zilic (Advances in Body Area Networks I, 2019)

A Structurally Regularized Convolutional Neural Network for Image Classification Using Wavelet-Based Subband Decomposition. - Pavel Sinha; Ioannis N. Psaromiligkos; Zeljko Zilic (ICIP, 2019)

Exploring Better Food Detection via Transfer Learning. - Jianing Sun; Katarzyna Radecka; Zeljko Zilic (MVA, 2019)

FoodTracker: A Real-time Food Detection Mobile Application by Deep Convolutional Neural Networks. - Jianing Sun; Katarzyna Radecka; Zeljko Zilic (CoRR, 2019)

A baseband processing ASIC for body area networks. - Junchao Wang; Kaining Han; Anastasios Alexandridis; Zeljko Zilic; Jinzhao Lin; Yu Pang; Xiaomin Yang (J. Ambient Intell. Humaniz. Comput., 2019)

Detecting Malicious Ethereum Entities via Application of Machine Learning Classification. - Farimah Poursafaei; Ghaith Bany Hamad; Zeljko Zilic (BRAINS, 2020)

Lumen & Media Segmentation of IVUS Images via Ellipse Fitting Using a Wavelet-Decomposed Subband CNN. - Pavel Sinha; Yimeng Wu; Ioannis N. Psaromiligkos; Zeljko Zilic (MLSP, 2020)

A blockchain-based eHealthcare system interoperating with WBANs. - Junchao Wang; Kaining Han; Anastasios Alexandridis; Zhiyu Chen; Zeljko Zilic; Yu Pang; Gwanggil Jeon; Francesco Piccialli (Future Gener. Comput. Syst., 2020)

An Ultrasound-Based Biomedical System for Continuous Cardiopulmonary Monitoring: A Single Sensor for Multiple Information. - Amirhossein Shahshahani; Zeljko Zilic; Sharmistha Bhadra (IEEE Trans. Biomed. Eng., 2020)

Energy and Task-Aware Partitioning on Single-ISA Clustered Heterogeneous Processors. - Ashraf Suyyagh; Zeljko Zilic (IEEE Trans. Parallel Distributed Syst., 2020)

Making Case for Using RAFT in Healthcare Through Hyperledger Fabric. - Anastasios Alexandridis; Ghassan Al-Sumaidaee; Rami Alkhudary; Zeljko Zilic (IEEE BigData, 2021)

SigTran: Signature Vectors for Detecting Illicit Activities in Blockchain Transaction Networks. - Farimah Poursafaei; Reihaneh Rabbany; Zeljko Zilic (PAKDD (1), 2021)

A Multistage Blockchain-Based Secure and Trustworthy Smart Healthcare System Using ECG Characteristic. - Junchao Wang; Shengwen Fan; Anastasios Alexandridis; Kaining Han; Gwanggil Jeon; Zeljko Zilic; Yu Pang (IEEE Internet Things Mag., 2021)

A Technical Assessment of Blockchain in Healthcare with a Focus on Big Data. - Ghassan Al-Sumaidaee; Anastasios Alexandridis; Rami Alkhudary; Zeljko Zilic (IEEE Big Data, 2022)

Decentralized Storage for Big Data in Healthcare between Reality and Ambition: IPFS and Sia. - Ghassan Al-Sumaidaee; Rami Alkhudary; Zeljko Zilic (IEEE Big Data, 2022)

A Stylized Presence Detection System in the Era of Blockchain and Big Data. - Anastasios Alexandridis; Ghassan Al-Sumaidaee; Rami Alkhudary; Zeljko Zilic (IEEE Big Data, 2022)

Sleep Stage Detection on a Wearable Headband Using Deep Neural Networks. - Mian Hamza; Sharmistha Bhadra; Zeljko Zilic (GIOTS, 2022)

A Strong Node Classification Baseline for Temporal Graphs. - Farimah Poursafaei; Zeljko Zilic; Reihaneh Rabbany (SDM, 2022)

Wearable Vibrotactile System as an Assistive Technology Solution. - Majid Janidarmian; Atena Roshan Fekr; Katarzyna Radecka; Zeljko Zilic (Mob. Networks Appl., 2022)

An Evaluation Framework for Assessing IPFS Performance within a Blockchain-Based Healthcare System. - Ghassan Al-Sumaidaee; Rami Alkhudary; Zeljko Zilic; Andraws I. Swidan (Blockchain, 2023)

Non-Fungible Tokens (NFTs) as a Means for Blockchain Networks Integration in Healthcare. - Ghassan Al-Sumaidaee; Rami Alkhudary; Zeljko Zilic (BRAINS, 2023)

Quality-driven Design Methodology for PUFs in FPGAs for Secure IoT. - Xiangyun Wang; Yicheng Song; Katyayani Prakash; Zeljko Zilic; Tomas Langsetmo (ISQED, 2023)

An IoT Ecosystem Platform for the Evaluation of Blockchain Feasibility. - Anastasios Alexandridis; Ghassan Al-Sumaidaee; Zeljko Zilic; Gwanggil Jeon; Junchao Wang (IEEE Internet Things J., 2023)

Performance analysis of a private blockchain network built on Hyperledger Fabric for healthcare. - Ghassan Al-Sumaidaee; Rami Alkhudary; Zeljko Zilic; Andraws I. Swidan (Inf. Process. Manag., 2023)

Scheduling Sparse LEO Satellite Transmissions for Remote Water Level Monitoring. - Garrett Kinman; Zeljko Zilic; David Purnell (Sensors, 2023)

Automated Assertion Checker Generator and Information Flow Tracking for Security Verification. - Miguel Angel Alfaro Zapata; Amirhossein Shahshahani; Zeljko Zilic (ISQED, 2024)

Optimizing Auditory Immersion Safety on Edge Devices: An On-Device Sound Event Detection System. - Reza Amini Gougeh; Nu Zhang; Zeljko Zilic (Odyssey, 2024)

Sensing Data Concealment in NFTs: A Steganographic Model for Confidential Cross-Border Information Exchange. - Ghassan Al-Sumaidaee; Zeljko Zilic (Sensors, 2024)

Systematic Review of IoT-Based Solutions for User Tracking: Towards Smarter Lifestyle, Wellness and Health Management. - Reza Amini Gougeh; Zeljko Zilic (Sensors, 2024)

Contributions of K. C. Smith in Applications of Multiple-Valued Logic. - Zeljko Zilic (ISMVL, 2025)

An FPGA-based Emulation Process for Dynamic Quantum Circuits. - Yicheng Song; Zeljko Zilic (ISQED, 2025)

A Structurally Regularized CNN Architecture via Adaptive Subband Decomposition. - Pavel Sinha; Ioannis N. Psaromiligkos; Zeljko Zilic (IEEE Trans. Neural Networks Learn. Syst., 2025)