The VLSI Design of Winscale for Digital Image Scaling. - Chung-Chi Lin; Zeng-Chuan Wu; Wen-Kai Tsai; Ming-Hwa Sheu; Huann-Keng Chiang (IIH-MSP, 2007)

Real-time FPGA architecture of extended linear convolution for digital image scaling. - Chung-Chi Lin; Ming-Hwa Sheu; Huann-Keng Chiang; Wen-Kai Tsai; Zeng-Chuan Wu (FPT, 2008)

A Low-cost VLSI Design of Extended Linear Interpolation for Real Time Digital Image Processing. - Chung-Chi Lin; Ming-Hwa Sheu; Huann-Keng Chiang; Zeng-Chuan Wu; Jia-Yi Tu; Chia-Hung Chen (ICESS, 2008)

The efficient VLSI design of BI-CUBIC convolution interpolation for digital image processing. - Chung-Chi Lin; Ming-Hwa Sheu; Huann-Keng Chiang; Chishyan Liaw; Zeng-Chuan Wu (ISCAS, 2008)

An efficient convolution interpolation kernel for digital image scaling. - Chung-Chi Lin; Ming-Hwa Sheu; Huann-Keng Chiang; Chishyan Liaw; Zeng-Chuan Wu (IEICE Electron. Express, 2008)

An Efficient Architecture of Extended Linear Interpolation for Image Processing. - Chung-Chi Lin; Ming-Hwa Sheu; Huann-Keng Chiang; Chishyan Liaw; Zeng-Chuan Wu; Wen-Kai Tsai (J. Inf. Sci. Eng., 2010)