A novel layout placement structure to mitigate the multi-bit-upset in 6T-SRAM cell. - Xu Hui; Zeng Yun (IEICE Electron. Express, 2014)

Circuit and layout combination technique to enhance multiple nodes upset tolerance in latches. - Xu Hui; Zeng Yun (IEICE Electron. Express, 2015)

DICE-based test structure to measure the strength of charge sharing effect. - Xu Hui; Zeng Yun; Bin Liang (IEICE Electron. Express, 2015)

Fast stochastic dual coordinate descent algorithms for linearly constrained convex optimization. - Zeng Yun; Deren Han; Yansheng Su; Jiaxin Xie (CoRR, 2023)