Coupled Data Prefetch and Cache Partitioning Scheme for CPU-Accelerator System. - Zengshi Wang; Chao Fu; Jun Han 003 (ASICON, 2023)

Chimera: A co-simulation framework combining with gem5 and FPGA platform for efficient verification. - Chao Fu; Zengshi Wang; Jun Han 003 (FPL, 2024)

VLSUMaP: A High-Performance Matrix Processor with Virtually Expanded LSU Boosting HBM Bandwidth Utilization. - Xin Yang; Xinjie Kong; Kaixuan Wang; Xin Fan; Zikang Zhou; Zhuoyuan Yang; Zengshi Wang; Jun Han 003 (ACM Great Lakes Symposium on VLSI, 2025)