An Adjacent-Line-Merging Writeback Scheme for STT-RAM last-level caches. - Masayuki Sato 001; Zentaro Sakai; Ryusuke Egawa; Hiroaki Kobayashi (COOL Chips, 2017)

An Adjacent-Line-Merging Writeback Scheme for STT-RAM-Based Last-Level Caches. - Masayuki Sato 001; Yoshiki Shoji; Zentaro Sakai; Ryusuke Egawa; Hiroaki Kobayashi (IEEE Trans. Multi Scale Comput. Syst., 2018)