A Novel Priority-Allocated Scheme for Flow-Based Queue Managers. - Yang Guo; Zerun Li (HPCC/SmartCity/DSS, 2018)

A task-based multi-core allocation mechanism for packet acceleration. - Zerun Li; Yang Guo 003; Sheng Liu 001; Junyang Zhang (IEICE Electron. Express, 2018)

Practical AMC model based on SAE with various optimisation methods under different noise environments. - Zerun Li; Qinglin Wang; Weisong Liu; Qiang Xu; Zuocheng Xing; Yongzhong Li (IET Commun., 2020)

Area-Efficient Parallel Reconfigurable Stream Processor for Symmetric Cryptograph. - Yufei Zhu; Zuocheng Xing; Jinhui Xue; Zerun Li; Yifan Hu; Yang Zhang 026; Yongzhong Li (IEEE Access, 2021)

High Area-Efficient Parallel Encoder with Compatible Architecture for 5G LDPC Codes. - Yufei Zhu; Zuocheng Xing; Zerun Li; Yang Zhang 026; Yifan Hu (Symmetry, 2021)

Optimal Data Allocation for Graph Processing in Processing-in-Memory Systems. - Zerun Li; Xiaoming Chen 003; Yinhe Han 001 (ASP-DAC, 2022)

GraphRing: an HMC-ring based graph processing framework with optimized data movement. - Zerun Li; Xiaoming Chen 003; Yinhe Han 001 (DAC, 2022)

Convolutional Neural Network Accelerator for Compression Based on Simon k-means. - Mingjie Wei; Yunping Zhao; Jianzhuang Lu; Xiaowen Chen; Chen Li; Zerun Li (IJCNN, 2022)

Automatic Modulation Classification for MASK, MPSK, and MQAM Signals Based on Hierarchical Self-Organizing Map. - Zerun Li; Qinglin Wang; Yufei Zhu; Zuocheng Xing (Sensors, 2022)

FSPA: An FeFET-based Sparse Matrix-Dense Vector Multiplication Accelerator. - Xiaoyu Zhang 009; Zerun Li; Rui Liu; Xiaoming Chen 003; Yinhe Han 001 (DAC, 2023)

FeCrypto: Instruction Set Architecture for Cryptographic Algorithms Based on FeFET-Based In-Memory Computing. - Rui Liu; Xiaoyu Zhang 009; Zhiwen Xie; Xinyu Wang; Zerun Li; Xiaoming Chen 003; Yinhe Han 001; Minghua Tang (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2023)

TMiner: A Vertex-Based Task Scheduling Architecture for Graph Pattern Mining. - Zerun Li; Xiaoming Chen 003; Yinhe Han 001 (MICRO, 2024)

GAS: General-Purpose In-Memory-Computing Accelerator for Sparse Matrix Multiplication. - Xiaoyu Zhang 009; Zerun Li; Rui Liu; Xiaoming Chen 003; Yinhe Han 001 (IEEE Trans. Computers, 2024)

Crypto-DSEDA: A Domain-Specific EDA Flow for CiM-Based Cryptographic Accelerators. - Rui Liu; Zerun Li; Xiaoyu Zhang 009; Wanqian Li; Libo Shen; Rui Tang; Zhejian Luo; Xiaoming Chen 003; Yinhe Han 001; Minghua Tang (IEEE Des. Test, 2024)

In-Memory Computing Accelerator for Iterative Linear Algebra Solvers. - Rui Liu; Zerun Li; Xiaoyu Zhang 009; Xiaoming Chen 003; Yinhe Han 001; Minghua Tang (IEEE Comput. Archit. Lett., 2025)

Statistical significance of cluster membership for categorical data. - Lianyu Hu 001; Zerun Li; Junjie Dong; Mudi Jiang; Zengyou He (Eng. Appl. Artif. Intell., 2025)

Conjunction subspaces test for conformal and selective classification. - Zengyou He; Zerun Li; Junjie Dong; Xinying Liu; Mudi Jiang; Lianyu Hu 001 (Inf. Sci., 2025)

A Data-Centric Software-Hardware Co-Designed Architecture for Large-Scale Graph Processing. - Zerun Li; Xiaoming Chen 003; Yuxin Yang 002; Feng Min; Xiaoyu Zhang 009; Yinhe Han 001 (IEEE Trans. Computers, 2025)