Distance Associativity for High-Performance Energy-Efficient Non-Uniform Cache Architectures. - Zeshan Chishti; Michael D. Powell; T. N. Vijaykumar (MICRO, 2003)

Wire Delay is Not a Problem for SMT (In the Near Future). - T. N. Vijaykumar; Zeshan Chishti (ISCA, 2004)

Optimizing Replication, Communication, and Capacity Allocation in CMPs. - Zeshan Chishti; Michael D. Powell; T. N. Vijaykumar (ISCA, 2005)

Trading off Cache Capacity for Reliability to Enable Low Voltage Operation. - Chris Wilkerson; Hongliang Gao; Alaa R. Alameldeen; Zeshan Chishti; Muhammad M. Khellah; Shih-Lien Lu (ISCA, 2008)

Shapeshifter: Dynamically changing pipeline width and speed to address process variations. - Eric Chun; Zeshan Chishti; T. N. Vijaykumar (MICRO, 2008)

Optimal Power/Performance Pipeline Depth for SMT in Scaled Technologies. - Zeshan Chishti; T. N. Vijaykumar (IEEE Trans. Computers, 2008)

Improving cache lifetime reliability at ultra-low voltages. - Zeshan Chishti; Alaa R. Alameldeen; Chris Wilkerson; Wei Wu 024; Shih-Lien Lu (MICRO, 2009)

Trading Off Cache Capacity for Low-Voltage Operation. - Chris Wilkerson; Hongliang Gao; Alaa R. Alameldeen; Zeshan Chishti; Muhammad M. Khellah; Shih-Lien Lu (IEEE Micro, 2009)

Reducing cache power with low-cost, multi-bit error-correcting codes. - Chris Wilkerson; Alaa R. Alameldeen; Zeshan Chishti; Wei Wu 024; Dinesh Somasekhar; Shih-Lien Lu (ISCA, 2010)

Rank-aware cache replacement and write buffering to improve DRAM energy efficiency. - Ahmed M. Amin; Zeshan Chishti (ISLPED, 2010)

Energy-efficient cache design using variable-strength error-correcting codes. - Alaa R. Alameldeen; Ilya Wagner; Zeshan Chishti; Wei Wu 024; Chris Wilkerson; Shih-Lien Lu (ISCA, 2011)

Adaptive Cache Design to Enable Reliable Low-Voltage Operation. - Alaa R. Alameldeen; Zeshan Chishti; Chris Wilkerson; Wei Wu 024; Shih-Lien Lu (IEEE Trans. Computers, 2011)

Operating SECDED-based caches at ultra-low voltage with FLAIR. - Moinuddin K. Qureshi; Zeshan Chishti (DSN, 2013)

Coordinated refresh: Energy efficient techniques for DRAM refresh scheduling. - Ishwar Bhati; Zeshan Chishti; Bruce L. Jacob (ISLPED, 2013)

Improving DRAM performance by parallelizing refreshes with accesses. - Kevin Kai-Wei Chang; Donghyuk Lee; Zeshan Chishti; Alaa R. Alameldeen; Chris Wilkerson; Yoongu Kim; Onur Mutlu (HPCA, 2014)

Sandbox Prefetching: Safe run-time evaluation of aggressive prefetchers. - Seth H. Pugsley; Zeshan Chishti; Chris Wilkerson; Peng-fei Chuang; Robert L. Scott; Aamer Jaleel; Shih-Lien Lu; Kingsum Chow; Rajeev Balasubramonian (HPCA, 2014)

Transparent Hardware Management of Stacked DRAM as Part of Memory. - Jaewoong Sim; Alaa R. Alameldeen; Zeshan Chishti; Chris Wilkerson; Hyesoon Kim (MICRO, 2014)

Flexible auto-refresh: enabling scalable and energy-efficient DRAM refresh reductions. - Ishwar Bhati; Zeshan Chishti; Shih-Lien Lu; Bruce L. Jacob (ISCA, 2015)

Bringing Modern Hierarchical Memory Systems Into Focus: A study of architecture and workload factors on system performance. - Paul Tschirhart; Jim Stevens; Zeshan Chishti; Shih-Lien Lu; Bruce L. Jacob (MEMSYS, 2015)

Efficiently prefetching complex address patterns. - Manjunath Shevgoor; Sahil Koladiya; Rajeev Balasubramonian; Chris Wilkerson; Seth H. Pugsley; Zeshan Chishti (MICRO, 2015)

The Case for Associative DRAM Caches. - Paul Tschirhart; Jim Stevens; Zeshan Chishti; Bruce L. Jacob (MEMSYS, 2016)

Path confidence based lookahead prefetching. - Jinchun Kim; Seth H. Pugsley; Paul V. Gratz; A. L. Narasimha Reddy; Chris Wilkerson; Zeshan Chishti (MICRO, 2016)

Reducing Performance Impact of DRAM Refresh by Parallelizing Refreshes with Accesses. - Kevin Kai-Wei Chang; Donghyuk Lee; Zeshan Chishti; Alaa R. Alameldeen; Chris Wilkerson; Yoongu Kim; Onur Mutlu (CoRR, 2016)

DRAM Refresh Mechanisms, Penalties, and Trade-Offs. - Ishwar Bhati; Mu-Tien Chang; Zeshan Chishti; Shih-Lien Lu; Bruce L. Jacob (IEEE Trans. Computers, 2016)

Hardware-Software Co-design to Mitigate DRAM Refresh Overheads: A Case for Refresh-Aware Process Scheduling. - Jagadish B. Kotra; Narges Shahidi; Zeshan A. Chishti; Mahmut T. Kandemir (ASPLOS, 2017)

Improving DRAM Performance by Parallelizing Refreshes with Accesses. - Kevin K. Chang; Donghyuk Lee; Zeshan Chishti; Alaa R. Alameldeen; Chris Wilkerson; Yoongu Kim; Onur Mutlu (CoRR, 2017)

Flexible associativity for DRAM caches. - Elvira Teran; Zeshan Chishti; Zhe Wang 023; Chris Wilkerson; Daniel A. Jiménez (CF, 2018)

Reducing DRAM Refresh Overheads with Refresh-Access Parallelism. - Kevin K. Chang; Donghyuk Lee; Zeshan Chishti; Alaa R. Alameldeen; Chris Wilkerson; Yoongu Kim; Onur Mutlu (CoRR, 2018)

TicToc: Enabling Bandwidth-Efficient DRAM Caching for Both Hits and Misses in Hybrid Memory Systems. - Vinson Young; Zeshan A. Chishti; Moinuddin K. Qureshi (ICCD, 2019)

Memory system characterization of deep learning workloads. - Zeshan Chishti; Berkin Akin (MEMSYS, 2019)

ZCOMP: Reducing DNN Cross-Layer Memory Footprint Using Vector Extensions. - Berkin Akin; Zeshan A. Chishti; Alaa R. Alameldeen (MICRO, 2019)

SAGA-Bench: Software and Hardware Characterization of Streaming Graph Analytics Workloads. - Abanti Basak; Jilan Lin; Ryan Lorica; Xinfeng Xie; Zeshan Chishti; Alaa R. Alameldeen; Yuan Xie 001 (ISPASS, 2020)

Improving Streaming Graph Processing Performance using Input Knowledge. - Abanti Basak; Zheng Qu; Jilan Lin; Alaa R. Alameldeen; Zeshan Chishti; Yufei Ding 001; Yuan Xie 001 (MICRO, 2021)

Architectural Support for Efficient Data Movement in Fully Disaggregated Systems. - Christina Giannoula; Kailong Huang; Jonathan Tang; Nectarios Koziris; Georgios I. Goumas; Zeshan Chishti; Nandita Vijaykumar (SIGMETRICS (Abstracts), 2023)

DaeMon: Architectural Support for Efficient Data Movement in Disaggregated Systems. - Christina Giannoula; Kailong Huang; Jonathan Tang; Nectarios Koziris; Georgios I. Goumas; Zeshan Chishti; Nandita Vijaykumar (CoRR, 2023)

Architectural Support for Efficient Data Movement in Disaggregated Systems. - Christina Giannoula; Kailong Huang; Jonathan Tang; Nectarios Koziris; Georgios I. Goumas; Zeshan Chishti; Nandita Vijaykumar (CoRR, 2023)

DaeMon: Architectural Support for Efficient Data Movement in Fully Disaggregated Systems. - Christina Giannoula; Kailong Huang; Jonathan Tang; Nectarios Koziris; Georgios I. Goumas; Zeshan Chishti; Nandita Vijaykumar (Proc. ACM Meas. Anal. Comput. Syst., 2023)