An 8-bit 1.5-GS/s Two-Step SAR ADC With Embedded Interstage Gain. - Yi Shen 007; Junyan Hao; Shubin Liu; Zeshuai An; Dengquan Li; Ruixue Ding; Zhangming Zhu (IEEE Trans. Very Large Scale Integr. Syst., 2023)