PipeNTT: A Pipelined Number Theoretic Transform Architecture. - Zewen Ye; Ray C. C. Cheung; Kejie Huang (IEEE Trans. Circuits Syst. II Express Briefs, 2022)

A Folded Computation-in-Memory Accelerator for Fast Polynomial Multiplication in BIKE. - Chuhui Wang; Zewen Ye; Haibin Shen; Kejie Huang (Euro-Par (2), 2024)

MVQ:Towards Efficient DNN Compression and Acceleration with Masked Vector Quantization. - Shuaiting Li; Chengxuan Wang; Juncan Deng; Zeyu Wang 010; Zewen Ye; Zongsheng Wang; Haibin Shen; Kejie Huang (CoRR, 2024)

HTCNN: High-Throughput Batch CNN Inference with Homomorphic Encryption for Edge Computing. - Zewen Ye; Tianshun Huang; Tianyu Wang; Yonggen Li; Chengxuan Wang; Ray C. C. Cheung; Kejie Huang (IACR Cryptol. ePrint Arch., 2024)

A Highly-efficient Lattice-based Post-Quantum Cryptography Processor for IoT Applications. - Zewen Ye; Ruibing Song; Hao Zhang; Donglong Chen; Ray Chak-Chung Cheung; Kejie Huang (IACR Trans. Cryptogr. Hardw. Embed. Syst., 2024)

ProgramGalois: A Programmable Generator of Radix-4 Discrete Galois Transformation Architecture for Lattice-Based Cryptography. - Guangyan Li; Zewen Ye; Donglong Chen; Wangchen Dai; Gaoyu Mao; Kejie Huang; Ray C. C. Cheung (ACM Trans. Reconfigurable Technol. Syst., 2024)

MVQ: Towards Efficient DNN Compression and Acceleration with Masked Vector Quantization. - Shuaiting Li; Chengxuan Wang; Juncan Deng; Zeyu Wang 010; Zewen Ye; Zongsheng Wang; Haibin Shen; Kejie Huang (ASPLOS (1), 2025)

FastViT: Real-Time Linear Attention Accelerator for Dense Predictions of Vision Transformer (ViT). - Zhuoheng Ran; Zewen Ye; Chong Wu; Ray C. C. Cheung; Hong Yan 001 (ISCAS, 2025)

Accelerating Prefilling for Long-Context LLMs via Sparse Pattern Sharing. - Dan Peng; Zhihui Fu; Zewen Ye; Zhuoran Song; Jun Wang (CoRR, 2025)

PQNTRU: Acceleration of NTRU-Based Schemes via Customized Post-Quantum Processor. - Zewen Ye; Junhao Huang 001; Tianshun Huang; Yudan Bai; Jinze Li; Hao Zhang; Guangyan Li; Donglong Chen; Ray C. C. Cheung; Kejie Huang (IEEE Trans. Computers, 2025)

RVSLH: Acceleration of Postquantum Standard SLH-DSA With Customized RISC-V Processor. - Zewen Ye; Xin Li; Chuhui Wang; Ray C. C. Cheung; Kejie Huang (IEEE Trans. Very Large Scale Integr. Syst., 2025)