Design reflection for optimal test-chip implementation. - R. D. (Shawn) Blanton; Benjamin Niewenhuis; Zeye (Dexter) Liu (ITC, 2015)

Achieving 100% cell-aware coverage by design. - Zeye Liu 001; Ben Niewenhuis; Soumya Mittal; R. D. (Shawn) Blanton (DATE, 2016)

Logic characterization vehicle design reflection via layout rewiring. - Phillip Fynan; Zeye Liu 001; Benjamin Niewenhuis; Soumya Mittal; Marcin Strajwas; R. D. (Shawn) Blanton (ITC, 2016)

Test chip design for optimal cell-aware diagnosability. - Soumya Mittal; Zeye Liu 001; Ben Niewenhuis; R. D. (Shawn) Blanton (ITC, 2016)

LightNN: Filling the Gap between Conventional Deep Neural Networks and Binarized Networks. - Ruizhou Ding; Zeye Liu 001; Rongye Shi; Diana Marculescu; R. D. (Shawn) Blanton (ACM Great Lakes Symposium on VLSI, 2017)

Front-end layout reflection for test chip design. - Zeye Liu 001; Phillip Fynan; Ronald D. Blanton (ITC, 2017)

Quantized deep neural networks for energy efficient hardware-based inference. - Ruizhou Ding; Zeye Liu 001; R. D. (Shawn) Blanton; Diana Marculescu (ASP-DAC, 2018)

CompactNet: High Accuracy Deep Neural Network Optimized for On-Chip Implementation. - Abhinav Goel; Zeye Liu 001; Ronald D. Blanton (IEEE BigData, 2018)

Back-End Layout Reflection for Test Chip Design. - Zeye Liu 001; Ronald D. Blanton (ICCD, 2018)

Lightening the Load with Highly Accurate Storage- and Energy-Efficient LightNNs. - Ruizhou Ding; Zeye Liu 001; R. D. (Shawn) Blanton; Diana Marculescu (ACM Trans. Reconfigurable Technol. Syst., 2018)

Regularizing Activation Distribution for Training Binarized Deep Networks. - Ruizhou Ding; Ting-Wu Chin; Zeye Liu 001; Diana Marculescu (CVPR, 2019)

FLightNNs: Lightweight Quantized Deep Neural Networks for Fast and Accurate Inference. - Ruizhou Ding; Zeye Liu 001; Ting-Wu Chin; Diana Marculescu; R. D. (Shawn) Blanton (DAC, 2019)

IPSA: Integer Programming via Sparse Approximation for Efficient Test-Chip Design. - Qicheng Huang; Chenlei Fang; Zeye Liu 001; Ruizhou Ding; R. D. Shawn Blanton (ICCD, 2019)

Characterization of Locked Sequential Circuits via ATPG. - Danielle Duvalsaint; Zeye Liu 001; Ananya Ravikumar; Ronald D. Blanton (ITC-Asia, 2019)

Improving Test Chip Design Efficiency via Machine Learning. - Zeye Liu 001; Qicheng Huang; Chenlei Fang; R. D. (Shawn) Blanton (ITC, 2019)

Path Delay Test of the Carnegie Mellon Logic Characterization Vehicle. - Ben Niewenhuis; Balaji Ravikumar; Zeye Liu 001; R. D. Shawn Blanton (VTS, 2019)

High Defect-Density Yield Learning using Three-Dimensional Logic Test Chips. - Zeye Liu 001; R. D. Shawn Blanton (ITC, 2020)

Efficient Test Chip Design via Smart Computation. - Chenlei Fang; Qicheng Huang; Zeye Liu 001; Ruizhou Ding; Ronald D. Blanton (ACM Trans. Design Autom. Electr. Syst., 2023)