A low cost test pattern generator for test-per-clock BIST scheme. - Shaochong Lei; Zhen Wang; Zeye Liu 002; Feng Liang (IEICE Electron. Express, 2010)

A unified solution to reduce test power and test volume for Test-per-scan schemes. - Shaochong Lei; Zhen Wang; Zeye Liu 002; Feng Liang (IEICE Electron. Express, 2010)

A Low Power Test Pattern Generator for BIST. - Shaochong Lei; Feng Liang; Zeye Liu 002; Xiaoying Wang; Zhen Wang (IEICE Trans. Electron., 2010)