Zeye Liu

According to our database, Zeye Liu authored at least 18 papers between 2015 and 2023.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2023

Efficient Test Chip Design via Smart Computation.

Chenlei Fang, Qicheng Huang, Zeye Liu, Ruizhou Ding, Ronald D. Blanton

ACM Trans. Design Autom. Electr. Syst., March, 2023

2020

High Defect-Density Yield Learning using Three-Dimensional Logic Test Chips.

Zeye Liu, R. D. Shawn Blanton

Proceedings of the IEEE International Test Conference, 2020

2019

Path Delay Test of the Carnegie Mellon Logic Characterization Vehicle.

Ben Niewenhuis, Balaji Ravikumar, Zeye Liu, R. D. Shawn Blanton

Proceedings of the 37th IEEE VLSI Test Symposium, 2019

Improving Test Chip Design Efficiency via Machine Learning.

Zeye Liu, Qicheng Huang, Chenlei Fang, R. D. (Shawn) Blanton

Proceedings of the IEEE International Test Conference, 2019

Characterization of Locked Sequential Circuits via ATPG.

Danielle Duvalsaint, Zeye Liu, Ananya Ravikumar, Ronald D. Blanton

Proceedings of the IEEE International Test Conference in Asia, 2019

IPSA: Integer Programming via Sparse Approximation for Efficient Test-Chip Design.

Qicheng Huang, Chenlei Fang, Zeye Liu, Ruizhou Ding, R. D. Shawn Blanton

Proceedings of the 37th IEEE International Conference on Computer Design, 2019

FLightNNs: Lightweight Quantized Deep Neural Networks for Fast and Accurate Inference.

Ruizhou Ding, Zeye Liu, Ting-Wu Chin, Diana Marculescu, R. D. (Shawn) Blanton

Proceedings of the 56th Annual Design Automation Conference 2019, 2019

Regularizing Activation Distribution for Training Binarized Deep Networks.

Ruizhou Ding, Ting-Wu Chin, Zeye Liu, Diana Marculescu

Proceedings of the IEEE Conference on Computer Vision and Pattern Recognition, 2019

2018

Lightening the Load with Highly Accurate Storage- and Energy-Efficient LightNNs.

Ruizhou Ding, Zeye Liu, R. D. (Shawn) Blanton, Diana Marculescu

ACM Trans. Reconfigurable Technol. Syst., 2018

Back-End Layout Reflection for Test Chip Design.

Zeye Liu, Ronald D. Blanton

Proceedings of the 36th IEEE International Conference on Computer Design, 2018

CompactNet: High Accuracy Deep Neural Network Optimized for On-Chip Implementation.

Abhinav Goel, Zeye Liu, Ronald D. Blanton

Proceedings of the IEEE International Conference on Big Data (IEEE BigData 2018), 2018

Quantized deep neural networks for energy efficient hardware-based inference.

Ruizhou Ding, Zeye Liu, R. D. (Shawn) Blanton, Diana Marculescu

Proceedings of the 23rd Asia and South Pacific Design Automation Conference, 2018

2017

Front-end layout reflection for test chip design.

Zeye Liu, Phillip Fynan, Ronald D. Blanton

Proceedings of the IEEE International Test Conference, 2017

LightNN: Filling the Gap between Conventional Deep Neural Networks and Binarized Networks.

Ruizhou Ding, Zeye Liu, Rongye Shi, Diana Marculescu, R. D. (Shawn) Blanton

Proceedings of the on Great Lakes Symposium on VLSI 2017, 2017

2016

Test chip design for optimal cell-aware diagnosability.

Soumya Mittal, Zeye Liu, Ben Niewenhuis, R. D. (Shawn) Blanton

Proceedings of the 2016 IEEE International Test Conference, 2016

Logic characterization vehicle design reflection via layout rewiring.

Phillip Fynan, Zeye Liu, Benjamin Niewenhuis, Soumya Mittal, Marcin Strajwas, R. D. (Shawn) Blanton

Proceedings of the 2016 IEEE International Test Conference, 2016

Achieving 100% cell-aware coverage by design.

Zeye Liu, Ben Niewenhuis, Soumya Mittal, R. D. (Shawn) Blanton

Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016

2015

Design reflection for optimal test-chip implementation.

R. D. (Shawn) Blanton, Benjamin Niewenhuis, Zeye (Dexter) Liu

Proceedings of the 2015 IEEE International Test Conference, 2015